Local clock buffer (LCB) with asymmetric inductive peaking
Local clock buffer (LCB) with asymmetric inductive peaking
Local interconnect network transceiver driver
Locally asynchronous, block-level synchronous, configurable...
Locally asynchronous, pipeline-able logic circuits for true-sing
Logic activation circuit
Logic allocator for a programmable logic device
Logic and level conversion circuit
Logic architecture for single event upset immunity
Logic architecture for single event upset immunity
Logic array and dynamic logic method
Logic array circuits using silicon-on-insulator logic
Logic array devices having complex macro-cell architecture...
Logic array devices having complex macro-cell architecture...
Logic array having high frequency internal clocking
Logic array having interleaved logic planes
Logic array having multi-level logic planes
Logic based on the evolution of nonlinear dynamical systems
Logic based on the evolution of nonlinear dynamical systems
Logic basic cell