Logic array and dynamic logic method

Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor

Reexamination Certificate

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C326S119000

Reexamination Certificate

active

06946879

ABSTRACT:
A monotonic dynamic-static pseudo-NMOS logic circuit comprises a dynamic logic circuit having a clock input and having an output configured to be pre-charged high when a low clock signal is provided to the clock input; and a static logic circuit having a clock bar input and having an output configured to be precharged low when a high value of the complement of the clock signal is provided to the clock bar input. A logic gate array comprises a plurality of vertical ultrathin transistors coupled together.

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