Logic and level conversion circuit

Details Logic and level conversion circuit Logic and level conversion circuit

1996-04-02

1998-09-08

Hudspeth, David R.

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 83, H03K 190185

Patent

active

058049886

ABSTRACT:
Invertors 23 and 24 operating under a low source voltage receive a reset signal Vr and an input signal Va respectively. Outputs of invertors 23 and 24 are connected to gates of a pMOS transistor 3 and an nMOS transistor 54 respectively, which operate under a high source voltage. The pMOS transistor 3 and the nMOS transistor 54 are connected in series, operating under a high source voltage. The pMOS transistor 3 has a threshold voltage which is approximately equal to the low source voltage.

REFERENCES:
patent: 4677317 (1987-06-01), Sakuma
patent: 5113097 (1992-05-01), Lee
patent: 5136190 (1992-08-01), Chern et al.
patent: 5151619 (1992-09-01), Austin et al.
patent: 5406140 (1995-04-01), Wert et al.
patent: 5418474 (1995-05-01), Davis et al.
patent: 5451889 (1995-09-01), Heim et al.

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