Logic array circuits using silicon-on-insulator logic

Details Logic array circuits using silicon-on-insulator logic Logic array circuits using silicon-on-insulator logic

2001-08-20

2003-04-22

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S045000, C326S049000, C326S050000, C326S106000

Reexamination Certificate

active

06552566

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to the field of logic circuits and more specifically to a novel design methodology for achieving faster circuits with a more compact circuit layout.
BACKGROUND OF THE INVENTION
Designing small, fast, low-power, and reliable logic circuits is becoming more difficult with scaling. Integrated logic circuits on silicon on insulator (SOI) substrates are beginning to find increasing usage in an effort to achieve these goals. SOI refers to a silicon substrate where the top layer (in which the devices are fabricated) is separated from the “bulk” portion of the substrate by a insulator layer. This can be contrasted with bulk silicon substrates which have no buried insulator layer. In bulk CMOS circuits, NMOS transistors are fabricated in p-type wells and PMOS devices are formed in n-type wells with both well structures formed in the substrate. These well structures provide the electrical isolation required between the NMOS and PMOS transistors in CMOS logic circuits. The spacing requirement of these well structures for proper electrical isolation in bulk CMOS logic circuit fabrication has led to grouping of NMOS and PMOS transistors to maximize circuit density. In bulk CMOS circuits, basic transistor networks performing logic functions can be classified as the following three types: pull-up network (PUN), which conditionally forms a current path between the output node and the circuit power supply, pull-down network (PDN), which conditionally forms a current path between the output node and the circuit ground, and pass-transistor network (PTN), which conditionally forms a current path between the output node and the pass inputs. In general only PMOS transistors are used in a PUN, only NMOS transistors are used in a PDN, and only PMOS or only NMOS transistors are used in a PTN except for pass gate logic. In early NMOS logic circuits, both enhancement and depletion mode NMOS transistors were used as pull up devices. In these NMOS circuits however, the gate of the enhancement transistor was connected to a fixed voltage (usually the supply voltage) and the gate of the depletion transistor was connected to the output node.
In general, digital circuits can be divided into two groups, static and dynamic circuits. Dynamic circuits can be further subdivided into one-phase “domino” circuits, two-phase ratioed, and ratioless circuits. Ratioless dynamic circuits can be further divided into two-phase and four-phase circuits. Logic networks generally comprise combinational and sequential networks. Combinational networks comprise gates and programmable logic arrays, and sequential networks comprise latches, registers, counters, and read-write memory. Combinational logic networks operate without the need of any periodic clock signals. However all but the very smallest digital systems require sequential as well as combinational logic. As a practical matter, all systems employing sequential logic require the use of periodic clock signals for correctly synchronized operation. In static SOI logic circuits, combinational or sequential, clock signals are introduced only at normal gate inputs, identical to those used for logic inputs. In applications where circuit delay is important and where silicon area is at a premium, CMOS dynamic logic circuits are used. Dynamic gates require clock signals that perform a precharge function to reduce circuit delay.
Another class of logic circuits is array logic. Array logic refers broadly to the address decoders of memories, the programmable logic arrays, the programmable array logic, and the content addressable memories. Shown in
FIG. 1
is block diagram of a typical logic array circuit. In an array logic circuit the output signals
70
, output
1
to output
x
are functions of the input signals A
1
to A
n
30
with the functionality defined by the interconnection in the pull-down network
10
. The address input lines
30
are fed into an address predecoder
20
. This address predecoder
20
produces a number of address inputs
40
that are fed into the pull-down network (PDN)
10
. Typically, these address inputs
40
are fed to the gates of the MOS transistors that comprise the PDN
10
. The PDN
10
is also typically connected to the circuit ground. The PDN
10
provides a number of output lines that are connected to a number of pull-up networks (PUN)
50
resulting in a number of array output lines
70
.
Conventional SOI logic circuits are based on bulk CMOS logic with conventional SOI circuits and bulk CMOS circuits sharing the same circuit topology. This is the case for the static, dynamic, and array logic circuits and networks discussed above. Thus in conventional SOI logic circuits, only PMOS transistors are used in a PUN, only NMOS transistors are used in a PDN, and only PMOS or only NMOS transistors are used in a PTN except for complementary pass gate logic. This circuit layout and design methodology while optimized for bulk CMOS circuits does not take full advantage of the unique properties of SOI substrates. A new circuit design methodology is therefore required that fully utilizes the properties of SOI substrates for CMOS logic circuits.
SUMMARY OF THE INVENTION
The instant invention comprises array logic fabricated on SOI substrates. The unique nature of SOI substrates allows novel circuit configurations. In particular, an array logic circuit on a SOI substrate, comprising: a pull-down network comprising a plurality of rows wherein each row comprises a plurality of NMOS or PMOS transistors connected in parallel; a plurality of input address lines connected to the gates of said plurality of NMOS or PMOS transistors; a plurality of pull-up networks connected to said plurality of rows; and a plurality of output lines connected to common nodes of said pull-up networks and said plurality of rows. In addition, the pull-up network comprises a depletion mode NMOS transistor; the pull-up network comprises a precharge PMOS transistor with a clock input; and at least one of said MOS transistors in said pull-down network has a gate tied to a floating substrate body.
A further embodiment of the instant invention comprises; a pull-down network comprising a plurality of rows wherein each row comprises a plurality of NMOS or PMOS transistors connected in series; a plurality of input address lines connected to the gates of said plurality of NMOS or PMOS transistors; a plurality of pull-up networks connected to said plurality of rows; and a plurality of output lines connected to common nodes of said pull-up networks and said plurality of rows. In addition, the pull-up network comprises a depletion mode NMOS transistor; the pull-up network comprises a precharge PMOS transistor with a clock input; and at least one of said MOS transistors in said pull-down network has a gate tied to a floating substrate body.


REFERENCES:
patent: 5991225 (1999-11-01), Forbes et al.
patent: 6222788 (2001-04-01), Forbes et al.
patent: 6229342 (2001-05-01), Noble et al.

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