Locally asynchronous, block-level synchronous, configurable...

Details Locally asynchronous, block-level synchronous, configurable... Locally asynchronous, block-level synchronous, configurable...

2007-11-06

2007-11-06

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S037000, C326S104000, C326S127000

Reexamination Certificate

active

11323950

ABSTRACT:
Embodiments utilize analog sub-threshold circuits to perform Boolean logic and soft-gate logic. These analog circuits may be grouped into configurable logic blocks that are locally asynchronous, but block-level synchronous. The Boolean logic, or function, performed by these blocks may be configured by programming bits. Other embodiments are described and claimed.

REFERENCES:
patent: 6282559 (2001-08-01), Helfenstein et al.
patent: 2004/0136472 (2004-07-01), Vigoda et al.
Rajagopalan, Kamal, et al., “A Flexible Multiplication Unit for an FPGA Logic Block”,IEEE International Symposium on Circuits and Systems(ISCAS 2001), vol. 4, (2001), 546-549, no month.
Tang, Halyun, et al., “On the Architectural Level Design of FPGA”,EE241 Midterm Report—Professor Jan Rabaey, Spring, 1997, http://web.archive.org/web/20021115195250/http://bwrc.eecs.berkeley.edu/People/Grad—Students
ingzh/241/241midterm.html, (Archived Nov. 11, 2002), 4 pgs.

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