Logic architecture for single event upset immunity

Details Logic architecture for single event upset immunity Logic architecture for single event upset immunity

2001-05-11

2003-09-02

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Reliability

C326S119000, C326S013000, C326S027000, C365S156000

Reexamination Certificate

active

06614257

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to radiation-hardened circuitry. More particularly, this invention comprises a logic family architecture capable of maintaining output signal integrity in the presence of transient signals caused by radiation.
2. Description of the Background Art
Electronic systems deployed in outer space or orbital environments may be subject to bombardment by high-energy particles, for example, protons, alpha particles, and/or other types of cosmic rays. Such high-energy particles may induce signal errors and possibly damage circuitry. For example, during periods of high solar flare activity, or in orbital regions characterized by radiation belt anomalies, high-energy particle bombardment may render communication satellites temporarily or permanently unreliable.
When a high-energy particle impinges upon an integrated circuit, it ionizes the regions through which it travels. This ionization creates mobile charges in the vicinity of the particle's travel path, thereby generating a transient signal or pulse in the device. The transient pulse may produce a Single Event Upset (SEU), which is a random, soft (i.e., nondestructive) logic or signal error. An SEU may change critical data and/or alter program or processor state. Depending upon severity, a circuit, device, or system may require a power reset to recover from an SEU.
A variety of approaches for reducing or minimizing SEU susceptibility exist. Special integrated circuit fabrication techniques, such as Silicon-on-Insulator (SOI) processes, may reduce SEU susceptibility. However, special fabrication techniques are significantly more costly than standard integrated circuit manufacturing processes.
An SEU is less likely to occur if the magnitude of its associated transient pulse is significantly less than the magnitude of normal signals within a device. Larger devices generally operate using larger-magnitude signals. Hence, another way to minimize SEU susceptibility is through the use of large-area devices. Unfortunately, large-area circuitry is less area-efficient, necessitates higher manufacturing costs, and consumes more power than densely packed circuitry. As a result, large area circuitry suffers from significant drawbacks relative to outer space or orbital applications.
Another approach to reducing SEU susceptibility is known as Triple Modular Redundancy (TMR), which involves replicating independent logic gates or stages three times. Each stage provides an output to a voting circuit, which determines a final output state as that which is output by a majority of the stages. The redundancy that TMR requires unfortunately results in drawbacks similar to those for large-area circuitry.
Yet another approach toward minimizing SEU susceptibility is circuit design modification. Such modification involves duplication of storage elements and provision of state-restoring feedback paths.
FIG. 1
is a circuit diagram of an SEU immune storage cell that includes state-restoring feedback paths. The SEU immune storage cell may serve as a latch or flip flop, or an element within a memory.
Unfortunately, prior circuit design modifications for minimizing SEU susceptibility are generally directed toward sequential, latching, and/or storage elements, rather than fundamental logic structures. What is needed is a comprehensive logic architecture that provides SEU immunity with minimal circuit redundancy, and which may be manufactured using conventional integrated circuit fabrication techniques.
SUMMARY OF THE INVENTION
The present invention is a logic architecture that may provide SEU immunity. In one embodiment, the logic architecture comprises a dual path logic element coupled to a dual to single path converter. The dual path logic element may comprise a first and a second logic element, which may be logically, and possibly structurally, equivalent. Each of the first and second logic elements includes a set of inputs and an output.
The first and second logic elements are each coupled to receive input signals spanning redundant input signal sets, where corresponding input signals within a first and a second input signal set are identically valued in the absence of a radiation induced transient pulse. The input signals are coupled within the first and second logic elements in an interleaved manner. In particular, corresponding logic structures and/or gates within each of the first and second logic elements may be coupled to receive input signals from opposite input signal sets. Thus, a given logic structure within the first logic element may be coupled to receive particular input signals within the first input signal set, while an analogous logic structure within the second logic element may be coupled to receive corresponding input signals within the second input signal set.
A radiation event may produce a transient pulse that is superimposed or carried upon an input signal. In the event that a transient pulse affects a given input signal within the first input signal set, a logic structure within the first logic element, for example, may temporarily assert or output an undefined or incorrect value. The transient pulse, however, may not affect the corresponding input signal within the second input signal set, and hence an analogous logic structure within the second logic element continues to assert or output a correct logical value. Thus, the dual path logic element may output at least one correctly valued signal following an occurrence of a radiation induced transient pulse.
The dual to single path converter includes inputs and an output, and may be coupled to receive signals produced by the aforementioned first and second logic elements. The dual to single path converter may act as a filter relative to signal transitions, such that it maintains or holds a given output state when a signal present at its inputs experiences a transition due to a transient pulse.
In one embodiment, the dual to single path converter comprises a first inverter structure that is embedded within a current path of a second inverter structure. The first inverter structure may be coupled to receive an output of the first logic element, while the second inverter structure may be coupled to receive an output of the second logic element. An output of the dual to single path converter may be provided by the first inverter structure.
When the dual to single path converter receives identically valued input signals, both inverter structures are in an identical operational state, and thus the dual to single path converter asserts an output signal having a particular desired value. A transient pulse may cause a signal applied to an input of the dual to single path converter to experience a transition of sufficient magnitude to cause the inverter structure to which it is coupled to switch to an opposite operational state. As a result, current flow within or through the dual to single path converter may be temporarily interrupted. During this temporary interruption, the stray or parasitic capacitance present at the dual to single path converter's output node maintains the output signal in its most recent state. In one embodiment, the dual to single path converter corresponds to a Muller C-element.
Depending upon embodiment and/or implementation details, dual path logic elements may be cascaded prior to delivering signals to the dual to single path converter. Other logic gates and/or circuits, such as conventional inverters large enough to remain unaffected by a transient pulse, may also be incorporated into circuit paths that include a dual path logic element and/or a dual to single path converter.


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patent: PCT/US02/14932 (2002-08-01), None
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