Local clock buffer (LCB) with asymmetric inductive peaking

Details Local clock buffer (LCB) with asymmetric inductive peaking Local clock buffer (LCB) with asymmetric inductive peaking

2008-08-04

2010-11-23

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

Reexamination Certificate

active

07839175

ABSTRACT:
A Local Clock Buffer (LCB), an IC chip including registers, some of which may include master/slave latches, locally clocked by the LCB, e.g., providing a launch clock and a capture clock each with an identified critical edge. The LCB includes asymmetrically inductively peaked series connected logic gates (e.g., inverters and/or NAND gates), each with an inductor between gate devices and supply (Vdd) or ground. The series connected gates alternate between having the inductor located between gate devices and the supply and located between gate devices and ground, providing asymmetric inductive peaking to maintain the sharpness of the critical edges. Optionally, corresponding logic gates in multiple LCBs may share the same inductor. Asymmetric inductive peaking allows reducing LCB power without degrading performance.

REFERENCES:
patent: 7136622 (2006-11-01), Rofougaran et al.
patent: 2005/0104646 (2005-05-01), Restle
Author: Yamazaki et al, Title: a 25GHz Clock Buffer and a 50Gb/s 2:1 Selector in 90nm CMOS, Date: Jun. 2004, Publisher: IEEE International Solid State Circuit Conference, Pertinent pages: all pages including drawings.
Author: Daisuke Yamazaki et al; Title: A 25GHz Clock Buffer and a 50Gb/s 2:1 Selector in 90nm CMOS; Date: Jun. 2004; Publisher: IEEE.
Yamazaki et al, “A 25 GHz clock buffer and a 50 Gb/s 2:1 selector in 90 nm CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 240-241, Feb. 2004Yamazaki et al, “A 25 GHz clock buffer and a 50 Gb/s 2:1 selector in 90 nm CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 240-241, Feb. 2004.

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