I/O block for high performance memory interfaces

Details I/O block for high performance memory interfaces I/O block for high performance memory interfaces

2011-04-19

2011-04-19

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S093000, C326S038000, C365S230030, C365S189050, C711S164000, C713S400000

Reexamination Certificate

active

07928770

ABSTRACT:
I/O blocks include input, output, and output enable circuits for interfacing with memory devices. The input circuit includes registers for capturing a double data rate signal, converting it into single data rate signals, and resynchronizing the single data rate signals. Multiple devices may be accessible with each device potentially having a different clock signal for resynchronizing. Another clock signal may be used to align/synchronize resulting signals from multiple devices. The resynchronized single rate signals can be converted into half-rate data signals, and the four half-rate data signals can be provided to resources in the programmable device core. The input circuit also may provide a half-rate clock signal synchronized with the half-rate data signals to the programmable device core. The half rate clock signal can be derived from the full-rate clock signal using a data strobe signal, a full-rate clock signal, or a half-rate clock signal as an input.

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patent: 2001/0046163 (2001-11-01), Yanagawa
U.S. Appl. No. 11/040,324, Thorne.

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