I/O buffer architecture for programmable devices

Details I/O buffer architecture for programmable devices I/O buffer architecture for programmable devices

2006-06-13

2006-06-13

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S039000, C716S030000

Reexamination Certificate

active

07061269

ABSTRACT:
Programmable devices, such as FPGAs, are designed with I/O buffer architectures having (at least) three different types of I/O buffers: single-ended buffers with Peripheral Component Interconnect (PCI) clamps, single-ended buffers without PCI clamps, and differential buffers without PCI clamps. By distributing these different types of I/O buffers around the periphery of the device, a relatively low-cost device can be implemented with relatively small I/O buffers that collectively provide all of the I/O signaling functionality of prior-art devices that are implemented with relatively large, all-purpose I/O buffers, each of which supports the full range of I/O signaling options available on the device.

REFERENCES:
patent: 6472904 (2002-10-01), Andrews et al.
patent: 6577163 (2003-06-01), Waldrip et al.
Xilinx: “Spartan-3 1.2V FPGA Family: Functional Description DS099-2 (v1.2)” Jul. 11, 2003.
“Cyclone Architecture”,, Altera Corporation, Oct. 2003, pp. 2-1, 2-39 thru 2-55.
“Spartan-3 1.2V FPGA Family: Functional Description”, Xilinx, DS099-2 (v1.2), Jul. 11, 2003, Advance Product Specification, pp. 1-9.

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