I/O architecture/cell design for programmable logic device

Details I/O architecture/cell design for programmable logic device I/O architecture/cell design for programmable logic device

2000-03-31

2003-08-19

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S040000, C326S041000, C326S086000

Reexamination Certificate

active

06608500

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to programmable logic devices generally and, more particularly, to an I/O architecture/cell design for a programmable logic device.
BACKGROUND OF THE INVENTION
Traditionally there are two types of programmable logic architectures: complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). The CPLD can be constructed as a one-dimensional array of logic blocks made of 16 macrocells and a product term array connected through a single central interconnect scheme. The CPLD achieves high performance by being able to complete a complex logic function in a single pass of the logic array and has predictable timing by having every output or I/O pin connected to every logic block input through the central interconnect structure. The CPLD can be non-volatile by using an EEPROM process.
However, the architecture of the conventional CPLD has disadvantages. A complex process technology limits performance and increases cost. A high standby power limits capacity and applications. The conventional CPLD has no available on-chip RAM. The maximum capacity of the conventional CPLD is limited by interconnect structure performance, power, technology and die cost. The core voltages, I/O voltages, and I/O standards of the conventional CPLD are not flexible. The I/O cells need a synchronous output enable (OE) to support a synchronous circuit architecture with minimal bus latency (e.g., as found in NoBL™ SRAMs manufactured by Cypress Semiconductor Corp. or ZBT™ devices manufactured by Integrated Device Technology) memory.
An FPGA architecture is constructed from a two dimensional array of logic blocks called CLBs. The CLBs are made from 4-input look-up-tables (LUTs) and flip-flops. The LUTs can be used as distributed memory blocks. The CLBs are connected by a segmented interconnect structure. The FPGA architecture supports a low standby power and the LUTs can use a simple logic CMOS process. Since the two-dimensional array of CLBs and the segmented interconnect structure are scalable, the FPGA can achieve high densities.
However, the architecture of the FPGA has disadvantages. A volatile process requires a FLASH/EEPROM to be added to the design. The segmented routing architecture limits performance and makes timing unpredictable. Implementing a dual port or FIFO memory with LUTs is slow and inefficient. A complex “design-in-process” is required because the conventional FPGAs do not have predictable timing, short compile times, in-system-reprogrammability (e.g., ISR®, a registered Trademark of Cypress Semiconductor Corp.) or pin fixing. The core voltage of the conventional FPGA is (i) not flexible and (ii) driven by the current process. The conventional FPGA makes product migration very difficult and does not support full JTAG boundary scan and configuration.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising an input/output circuit and a programmable logic device. The input/output circuit may be configured to (i) connect to an end of a bus and (ii) operate in one or more modes in response to one or more control signals. The programmable logic device may be configured to generate said one or more control signals.
The objects, features and advantages of the present invention include providing a I/O architecture/cell design for a programmable logic device that may (i) have a simple timing model; (i) provide a STAPL interface to allow for a part to be reconfigured in-system; (iii) support a JTAG boundary scan (including INTEST) for easy debugging; (iv) support the basic I/O standards of JEDEC 1.8V, LVCMOS, LVCMOS2, LVTTL, 3.3V PCI, GTL+, HSTL class I through IV, SSTL2 Class I and II, and SSTL3 Class I and II; and/or (v) provide for combining I/O cells into I/O banks.


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