Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2002-03-14
2004-07-06
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S083000, C326S086000, C326S068000, C326S062000, C327S333000, C327S112000
Reexamination Certificate
active
06759872
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates generally to semiconductor integrated circuit (IC) devices and more particularly, it relates to input/output (I/O) circuits with mixed supply voltage capability.
In the semiconductor industry, power reduction, die size reduction and higher speed have been major driving forces in improving the performance of integrated circuits (ICs). In particular, low power ICs offer numerous advantages. For example, low power ICs allow high density devices to be manufactured, which are particularly suitable for mobile devices. The current trend is to reduce the standard supply voltage Vcc from 5V to 3.3V and even lower.
FIG. 1
shows a typical conventional high voltage input/output (I/O) circuit
10
in a low voltage technology. I/O circuit
10
includes a level shifter
4
, buffers
18
and
26
, a voltage reference circuit
12
, and an output stage
36
. I/O circuit
10
is powered by Vcc, which may be the standard 5V or a lower supply voltage of 3.3 V, and receives an input voltage Vin switching between 0-3.3V. Voltage reference circuit
12
provides reference voltages V
RP
and V
RN
to buffers
18
and
20
, respectively. The voltage across buffers
18
and
20
should generally stay within the maximum voltage the process can handle. In other words, the voltage differences between Vcc and V
RP
and between V
RN
and ground level should be less than the maximum voltage the process can handle. This usually means that in a 3.3V process VRP is around 1.7V (5.5-3.3V) and V
RN
is around 3.3V when Vcc is 5V. In the case Vcc is 5V, voltage input Vin of 0-3.3V is level shifted to 1.7-5V by level shifter
14
and is input to buffer
18
. Buffer
18
, which has a signal swing between V
RP
and Vcc, i.e., between 1.7 and 5V, outputs signals between 1.7-5V to output stage
36
. On the other hand, buffer
26
has a signal swing between a ground level and V
RN
, i.e., between 0 and 3.3V and outputs signals between 0-3.3V to output stage
36
. Output stage
36
then output signals between 0-5V.
I/O circuit
10
works properly when a 5V supply voltage is applied. However, I/O circuit
10
will not operate properly when a 3.3 supply voltage is applied. In the latter case, buffer
18
will have a smaller signal swing between 1.7 to 3.3V. Such a smaller signal swing causes the speed of I/O circuit
10
to become very slow such that it does not meet the high speed requirements of many applications. This is because for optimal operation of a CMOS circuit sufficient “headroom” is required. Headroom is the difference between the supply voltage to buffers
18
and
20
and threshold voltages of their transistors.
Therefore, there is a need for a driver circuit with superior performance.
SUMMARY OF THE INVENTION
The present invention provides a solution that addresses the limiting factors of the conventional I/O circuits. According to one embodiment of the invention, there is provided an I/O circuit to be powered by a supply voltage. The I/O circuit comprises a pair of buffers, each of which is responsive to input signals and configured to provide signals of sufficiently large signal swings to allow high speed operations; a voltage reference circuit, operably coupled to the pair of buffers, that is configured to provide first and second reference voltages to the pair of buffers respectively; and a detection circuit, operably coupled to voltage reference circuit, that is configured to detect whether the supply voltage is below a switching voltage. The switching voltage is a pre-selected value between operating ranges of two pre-defined supply voltages, which, for example, may be 3.3V and 5V, respectively. Alternatively, they may be 2.5V and 3.3V, respectively. If the supply voltage is below the switching voltage, the detection circuit controls the voltage reference circuit to set the first and second reference voltages to first and second predetermined values, respectively. According to one embodiment of the invention, the first and second predetermined values are a ground level and the supply voltage, respectively. In this way, the large signal swings of the signals output by the buffers can be substantially maintained. Therefore, the high speed operations can be achieved.
Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5894423 (1999-04-01), Ling et al.
patent: 6323704 (2001-11-01), Pelley et al.
Marcel J.M. Pelgrom and E.Carel Dijkmans, “A 3/5 V Compatible I/O Buffer”, IEEE Journal of Solid State Circuits, No. 7, Jul. 1995, pp. 823-825, vol. 30.
de Vries Ronald
Lai Eric
Koninklijke Philips Electronics , N.V.
Tan Vibol
Waxler Aaron
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