I/O buffer circuit with pin multiplexing

Details I/O buffer circuit with pin multiplexing I/O buffer circuit with pin multiplexing

1997-07-16

2000-02-01

Santamauro, Jon

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 37, 326 38, 326 93, H03K 19173, H03K 19177

Patent

active

060207604

ABSTRACT:
An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has flexible input/output buffer circuits. These input/output buffer circuits transfer data either bidirectionally or unidirectionally between an input/output pin and a FPGA core. Each input/output buffer circuit allows at least two signals to be time-multiplexed onto an input/output pin thereby doubling the effective input/output capacity. The input/output buffer circuits may be used to time-multiplex at least two signals onto an input pin, at least two signals onto an output pin, or both. Each input/output buffer circuit further has shared flip flops for time-multiplexing signals. The circuitry provides two connections into the FPGA core which can be used to time-multiplex at least two independent inputs or outputs.

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