Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2011-01-11
2011-01-11
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S086000, C327S108000, C327S333000
Reexamination Certificate
active
07868659
ABSTRACT:
The invention relates to an I/O buffer with twice the supply voltage tolerance using normal supply voltage devices. The I/O buffer of the invention includes a driver, a first level converter, a gate-controlled circuit and a dynamic source output stage. Signals of the I/O buffer are classified into a first voltage range and a second voltage range. The first voltage range is zero to the normal supply voltage, and the second voltage range is the normal supply voltage to twice the supply voltage. Therefore, the voltage between any two terminals of any of the transistors in the I/O buffer does not exceed the normal supply voltage so that the I/O buffer of the invention can transmit and receive signals with a voltage swing twice as high as the normal power supply voltage using normal supply voltage devices and without gate-oxide reliability problems.
REFERENCES:
patent: 5604449 (1997-02-01), Erhart et al.
patent: 5684415 (1997-11-01), McManus
patent: 5712586 (1998-01-01), Kitao
patent: 5834948 (1998-11-01), Yoshizaki et al.
patent: 5896045 (1999-04-01), Siegel et al.
patent: 6040729 (2000-03-01), Sanchez et al.
patent: 6057710 (2000-05-01), Singh
patent: 6064227 (2000-05-01), Saito
patent: 6064230 (2000-05-01), Singh
patent: 6130557 (2000-10-01), Drapkin et al.
patent: 6229365 (2001-05-01), Iketani et al.
patent: 6268744 (2001-07-01), Drapkin et al.
patent: 6388470 (2002-05-01), Mattos et al.
patent: 6392440 (2002-05-01), Nebel
patent: 6429716 (2002-08-01), Drapkin et al.
patent: 6509759 (2003-01-01), Hynes
patent: 6577163 (2003-06-01), Waldrip et al.
patent: 6768368 (2004-07-01), Kaneko et al.
patent: 6833746 (2004-12-01), Drapkin et al.
patent: 6859074 (2005-02-01), Ajit
patent: 6870407 (2005-03-01), Lundberg
patent: 6975134 (2005-12-01), Kuang et al.
patent: 7088167 (2006-08-01), Itoh
patent: 7135914 (2006-11-01), Chih et al.
patent: 7215146 (2007-05-01), Khan
patent: 7224195 (2007-05-01), Pilling et al.
patent: 7362136 (2008-04-01), Chen
patent: 7560970 (2009-07-01), Cook et al.
patent: 7570088 (2009-08-01), Ku et al.
patent: 7573314 (2009-08-01), Nagayama
patent: 7586343 (2009-09-01), Pilling et al.
patent: 7777522 (2010-08-01), Yang et al.
patent: 2002/0011873 (2002-01-01), Riccio et al.
patent: 2002/0024359 (2002-02-01), Chan et al.
patent: 2002/0093362 (2002-07-01), Matsumoto
patent: 2005/0040852 (2005-02-01), Mentze et al.
patent: 2005/0040854 (2005-02-01), Mentze et al.
patent: 2005/0156631 (2005-07-01), Huang
patent: 2005/0258864 (2005-11-01), Chen et al.
patent: 2006/0033529 (2006-02-01), Chauhan et al.
patent: 2006/0091907 (2006-05-01), Khan
patent: 2007/0052445 (2007-03-01), Wu et al.
patent: 2008/0231322 (2008-09-01), Mohammad et al.
Ker Ming-Dou
Lin Yan-Liang
Wang Chua-Chin
Cho James H.
Muncy Geissler Olds & Lowe, PLLC
National Sun Yat-Sen University
Tabler Matthew C
LandOfFree
I/O buffer with twice the supply voltage tolerance using... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with I/O buffer with twice the supply voltage tolerance using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and I/O buffer with twice the supply voltage tolerance using... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2661539