I/O cell configuration for multiple I/O standards

Details I/O cell configuration for multiple I/O standards I/O cell configuration for multiple I/O standards

2006-04-25

2006-04-25

Le, Don (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S082000

Reexamination Certificate

active

07034570

ABSTRACT:
Circuitry is provided to individually configure each I/O of an integrated circuit to be compatible with a different LVTTL I/O standards. This can be done with only one I/O supply voltage, where that voltage is the highest of the I/O voltages needed in a particular application. The circuitry operates by regulating the output voltage of the I/O cell so that it is above the VOH and below the maximum VIH for the LVTTL standard for which it will comply with. Since each I/O cell is individually configurable, any I/O can drive out to any LVTTL specification.

REFERENCES:
patent: 4032800 (1977-06-01), Droscher et al.
patent: 4469959 (1984-09-01), Luke et al.
patent: 4472647 (1984-09-01), Allgood et al.
patent: 4527079 (1985-07-01), Thompson
patent: 4625129 (1986-11-01), Ueno
patent: 4742252 (1988-05-01), Agrawal
patent: 4783607 (1988-11-01), Hsieh
patent: 4791312 (1988-12-01), Weick
patent: 4797583 (1989-01-01), Ueno et al.
patent: 4820937 (1989-04-01), Hsieh
patent: 4879481 (1989-11-01), Pathak et al.
patent: 4933577 (1990-06-01), Wong et al.
patent: 4970410 (1990-11-01), Matsushita et al.
patent: 4975602 (1990-12-01), Nhu
patent: 4987319 (1991-01-01), Kawana
patent: 4994691 (1991-02-01), Naghshineh
patent: 4999529 (1991-03-01), Morgan, Jr. et al.
patent: 5023488 (1991-06-01), Gunning
patent: 5028821 (1991-07-01), Kaplinsky
patent: 5034634 (1991-07-01), Yamamoto
patent: 5132573 (1992-07-01), Tsuru et al.
patent: 5151619 (1992-09-01), Austin et al.
patent: 5235219 (1993-08-01), Cooperman et al.
patent: 5282271 (1994-01-01), Hsieh et al.
patent: 5300835 (1994-04-01), Assar et al.
patent: 5311080 (1994-05-01), Britton et al.
patent: 5317210 (1994-05-01), Patel
patent: 5331220 (1994-07-01), Pierce et al.
patent: 5332935 (1994-07-01), Shyu
patent: 5369317 (1994-11-01), Casper et al.
patent: RE34808 (1994-12-01), Hsieh
patent: 5374858 (1994-12-01), Elmer
patent: 5428305 (1995-06-01), Wong et al.
patent: 5428800 (1995-06-01), Hsieh et al.
patent: 5440249 (1995-08-01), Schucker et al.
patent: 5521530 (1996-05-01), Yao et al.
patent: 5534794 (1996-07-01), Moreland
patent: 5534798 (1996-07-01), Phillips et al.
patent: 5583454 (1996-12-01), Hawkins et al.
patent: 5589783 (1996-12-01), McClure
patent: 5606275 (1997-02-01), Farahang et al.
patent: 5612637 (1997-03-01), Shay et al.
patent: 5689460 (1997-11-01), Ooishi et al.
patent: 5798659 (1998-08-01), Shay et al.
patent: 5815013 (1998-09-01), Johnston
patent: 5880624 (1999-03-01), Koyanagi et al.
patent: 5974476 (1999-10-01), Lin et al.
patent: 6018252 (2000-01-01), Imaizumi
patent: 6404712 (2000-03-01), Mejia
patent: 6049227 (2000-04-01), Goetting et al.
patent: 6163180 (2000-12-01), Hidaka et al.
patent: 6229365 (2001-05-01), Iketani et al.
patent: 6271679 (2001-08-01), McClintock et al.
patent: 6271879 (2001-08-01), McClintock et al.
patent: 6335637 (2002-01-01), Correale, Jr. et al.
patent: 6714050 (2004-03-01), McClintock et al.
patent: 6836151 (2004-12-01), McClintock et al.
patent: 0 358 501 (1990-03-01), None
patent: 0 544 461 (1993-02-01), None
patent: 0 608 515 (1994-03-01), None
patent: 0 616 431 (1994-09-01), None
patent: 0718977 (1996-06-01), None
patent: 0750242 (1996-12-01), None
patent: 0 426 283 (1997-12-01), None
patent: 01-274512 (1989-11-01), None
patent: 02-013124 (1990-01-01), None
patent: 02-161820 (1990-06-01), None
patent: 04-223617 (1992-08-01), None
patent: WO 98/47230 (1998-10-01), None
Altera Corporation, Data Sheet, “Flex 10K Embedded Progrmmable Logic Family, ” Jul., 1995, ver. 1, pp. 1-39.
Altera Corporation, Data Sheet, “Apex 20K”, May, 1999, pp. 23-88.
Chappell et al. “Fast CMOS ECL Receivers With 100-mV Worst-Case Sensitivity,”IEEE Journal of Solid-State Circuits, vol. 23, No. 1, Feb. 1988, pp. 59-66.
Claude “Cross-boundary PLDs,”Semiconductor Currents, Jun., 1991, pp. 9-10.
Guardiani et al. “Applying a submicron mismatch model to practical IC design,”IEEE 1994 Custom Integrated Circuits Conference, 1994, pp. 297-300.
Gunning et al., “A CMOS Low-Voltage-Swing Transmission-Line Transceiver,”IEEE International Solid-State Circuits Conference, 1992, pp. 58-59.
Haines “Field-programmable gate array with non-volitile configuration,”Microprocessors and Microsystems, vol. 13, No. 5, Jun. 1989, pp. 305-312.
Hanafi et al. “Design and Characterization of CMOS Off-Chip Driver/Receiver with Reduced Power-Supply Disturbance,”IEEE Journal of Solid-State Circuits, vol. 27, No. 5, May 1992, pp. 783-785.
Martinez “IEEE 1194.1 BTL-Enabling Technology for High Speed Bus Applications,” National Semiconductor Application Note 829, Jun. 1992, pp. 1-5.
Knack “Debunking High-Speed PCB Design Myths,”ASIC & EDA, Jul. 1993, pp. 12-26.
Pelgrom et al. “A 3/5 V Compatible I/O Buffer,”IEEE Journal of Solid-State Circuits, vol. 30, No. 7, Jul. 1995, pp. 823-825.
Pelgrom et al. “Matching Properties of MOS Transistors,”IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1433-1440.
Prince et al. “ICs going on a 3-V diet,”IEEE Spectrum, May 1992, pp. 23-25.
Roberts et al. “Session XIX: High Density SRAMs,”IEEE International Solid-State Circuits Conference, Feb. 27, 1987, pp.252-254.
Senthinathan et al., “Application Specific CMOS Output Driver Circuit Design Techniques to Reduce Simultaneous Switching Noise,”IEEE Journal of Solid-State Circuits, vol. 28, No. 12, Dec. 1993, pp. 1383-1388.
Senthinathan et al., “Simultaneous Switching Ground Noise Calculation for Packaged CMOS Devices,”IEEE Journal of Solid-State Circuits,vol. 26, No. 11, Nov. 1991, pp. 1724-1728.
Ueda et al. “A 3.3V ASIC for Mixed Voltage Applications With Shut Down Mode,”IEEE 1993 Custom Integrated Circuits Conference, May 9-12, 1993, pp. 25.5.1 to 25.5.4.
Voldman “ESD Protections ina Mixed Voltage Interface and Multi-Rail Disconnected Power Grid Environment in 0.50- and 0.25-μm Channel Length CMOS Technologies,”EOS/ESD Symposium, 1994, PP. 3.4.1 to 3.4.10.
Vu et al. “A Gallium Arsenide SDFL Gate Array with On-Chip RAM,”IEEE Journal of Solid-State Circuits, vol. sc-19, No. 1, Feb. 1984, pp. 10-22.
Williams “Mixing 3-V and 5-V ICs,”IEEE Spectrum, Mar. 1993, pp. 40-42.
“Virtex 2.5 V Field Programmable Gate Arrays”; XILINX, Nov. 1998, 20 pages.

Affiliated with

Also associated with

Rating

I/O cell configuration for multiple I/O standards does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with I/O cell configuration for multiple I/O standards, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and I/O cell configuration for multiple I/O standards will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3547442