Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1999-12-13
2001-09-04
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S039000, C326S040000
Reexamination Certificate
active
06285211
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to input/output (I/O) buffer circuits, and is specifically directed to an I/O buffer circuit for a field programmable gate array wherein two logical signals are multiplexed onto each physical I/O pin of each I/O buffer circuit such that the I/O capacity of the FPGA is effectively doubled. I/O buffer circuits constructed in accordance with the present invention are thus applicable to FPGAs designed for use in hardware logic emulation systems.
BACKGROUND OF THE INVENTION
Field programmable gate arrays (FPGAs) are devices which can be arbitrarily programmed to implement a wide variety of logic circuit designs. An FPGA typically contains an array of logic blocks, each of which can be configured to perform selected logic functions in response to the programming of the FPGA. Individual logic blocks are configured to represent the individual elements of the logic circuit design being implemented. I/O pins on the FPGA carry data, control and clock signals to and from the configured logic blocks as required by the implemented circuit design.
The size of a circuit design which can be implemented in an FPGA depends on the number of logic blocks in the FPGA and the number of I/O pins available to the FPGA for use in implementing the circuit design. I/O pin count is a function of the perimeter dimension of the FPGA and the distance between I/O pads required by existing wirebonding equipment. Hence, the number of I/O pins on a given FPGA is proportional to die size, and only increases relatively slowly with advances in assembly equipment. The number of logic blocks which can be placed on an FPGA, however, is proportional to the square of the die size and is growing rapidly as the size of functional devices which can be fabricated on silicon continues to shrink. Continued reduction in the physical dimensions of integrated circuit devices such as FPGAs is therefore imposing a severe bottleneck with respect to I/O pin availability. Under these circumstances, it would be desirable to provide a means for reducing or avoiding the I/O availability bottleneck which otherwise limits the size of circuit designs which can be implemented in an FPGA.
SUMMARY OF THE INVENTION
The present invention time-multiplexes at least two signals onto a single input/output pin, thereby increasing the effective I/O capacity.
A first, separate aspect of the present invention is a design that maximizes the effective I/O pin availability in a field programmable gate array.
A second, separate aspect of the present invention is an efficient structure and technique for time-multiplexing signals on the I/O pins of a circuit used to implement reconfigurable logic.
A third, separate aspect of the present invention is an efficient structure and technique for transferring multiple input or output signals over a single I/O pin of a field programmable gate array.
A fourth, separate aspect of the present invention is an input/output buffer circuit that time-multiplexes signals onto an I/O pin and provides a delay element for adding delay to a signal as needed.
A fifth, separate aspect of the present invention is an input/output buffer circuit that provides two different paths from the I/O pin to the core and two different paths from the core to the I/O pin, both of which can be time-multiplexed.
In the preferred embodiment, these and other aspects of the present invention are achieved with a reconfigurable I/O buffer circuit which can be used in a field programmable gate array, wherein the buffer circuit is connected to the FPGA core via two circuit paths and drives one physical I/O pin. The I/O buffer circuit can be selectively configured in a manner which enables the two core circuit paths to provide bidirectional I/O capability. Alternately, the I/O buffer circuit of the present invention can be reconfigured to provide for time multiplexing of at least two input signals or two output signals onto the same physical I/O pin. Buffer circuit reconfigurability requires only two flip-flops in the I/O buffer circuit cell. The I/O buffer circuit can also swap signals between the two core connections to provide additional I/O routing flexibility.
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Butts Michael R.
Norman Kevin A.
Patel Rakesh H.
Sample Stephen P.
Altera Corporation
Paik Steven S.
Tokar Michael
Townsend and Townsend / and Crew LLP
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