Staggered I/O groups for integrated circuits
State splitting for level reduction
Static memory cell circuit with single bit line and...
Stored and combinational logic function generator without dedica
Structure and method for arithmetic function implementation in a
Structure and method for configuration of a field programmable g
Structure and method for implementing hierarchical routing pools
Structure and method for reading blocks of data from selectable
Structure for optionally cascading shift registers
Structure for reducing leakage current in submicron IC devices
Structured integrated circuit device
Structured integrated circuit device
Structured integrated circuit device
Structures and methods for distributing high-fanout signals...
Structures and methods for reducing power consumption in...
Structures and methods of implementing a pass gate...
Structures and methods providing columns of tightly coupled...
Structures and methods providing columns of tightly coupled...
Swap MUX to relieve logic device input line stress
Switch matrix circuit, logical operation circuit, and switch...