System and method for reducing power-on-transient current...
System and methods for a high-speed dynamic data bus
System level hardening of asynchronous combinational logic
Systems and methods for A 5:1 multiplexer with a one-fifth...
Systems and methods of integrated circuit clocking
Systems with skew control between clock and data signals
Teacher-pupil flip-flop
Technique for mitigating gate leakage during a sleep state
Techniques for reducing clock skew in clock routing networks
Techniques for reducing power requirements of an integrated...
Three-transistor NAND and NOR gates for two-phase clock...
Time multiplexed ratioed logic
Timing circuit utilizing a clock tree as a delay device
Transfer of digital data across asynchronous clock domains
Tri-rail domino circuit
Tunable clock distribution system for reducing power...
Two legged reset controller for domino circuit
Two-phase dynamic logic circuits for gallium arsenide complement
Two-phase dynamic logic circuits for gallium arsenide complement
Two-phase overlapping clocking technique for digital dynamic cir