Techniques for reducing power requirements of an integrated...

Details Techniques for reducing power requirements of an integrated... Techniques for reducing power requirements of an integrated...

2008-05-16

2009-10-20

Cho, James (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S136000, C327S544000, C713S322000

Reexamination Certificate

active

07605612

ABSTRACT:
A technique for clock gating a clock domain of an integrated circuit includes storing first, second, and third values in a control register. The first value corresponds to a first number of clock cycles to wait before initiating clock gating, the second value corresponds to a second number of clock cycles in which clock gating is performed, and the third value corresponds to a third number of clock cycles in which clock gating is not performed. One of the first, second, and third values is selectively loaded from the control register into a counting circuit. The counting circuit counts from the loaded one of the first, second, and third values to a transition value. A compare signal is received at the control state machine (from the counting circuit) that indicates the counting circuit has reached the transition value. Based on a current state of the control state machine, a load signal is provided to the counting circuit to cause the counting circuit to load an associated one of the first, second, and third values from the control register.

REFERENCES:
patent: 5583450 (1996-12-01), Trimberger et al.
patent: 6636074 (2003-10-01), Schulz
patent: 7095251 (2006-08-01), Wilcox et al.

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