Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2007-01-02
2007-01-02
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S095000, C365S203000
Reexamination Certificate
active
09888970
ABSTRACT:
A method for driving a data signal across a data bus consists of charging the data bus to a first voltage level prior to driving the signal, maintaining the data bus at the first voltage level when a first type of data signal is to be driven, and pulling the data bus to a second voltage level when a second type of data signal is to be driven. A system for driving a data signal consists of a data bus, a charging circuit coupled to the data bus configured to charge the data bus to a first voltage level, a keeper circuit coupled to the data bus configured to maintain the data bus at the first voltage level after the charging circuit has charged the data bus, and a pull-down circuit coupled to the data bus configured to pull the data bus to a second voltage level.
REFERENCES:
patent: 5544109 (1996-08-01), Uchida et al.
patent: 6320795 (2001-11-01), Balamurugan et al.
patent: 6388940 (2002-05-01), Alvandpour et al.
patent: 6456116 (2002-09-01), Coppin
Chang Daniel D.
Inapac Technology, Inc
Sidley Austin LLP
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