Technique for mitigating gate leakage during a sleep state

Details Technique for mitigating gate leakage during a sleep state Technique for mitigating gate leakage during a sleep state

2002-12-12

2004-09-14

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S034000, C327S544000

Reexamination Certificate

active

06791361

ABSTRACT:

TECHNICAL FIELD
The present invention relates to the field of power consumption in integrated circuits, and more particularly to mitigating transistor gate leakage during a sleep mode of integrated circuit operation.
BACKGROUND INFORMATION
The power consumption of an electronic device may be made up of two components. The dynamic power consumption relates to the power that is consumed when the device is operating. In connection with processors, the dynamic power consumption may occur when the processor's clocks are operating. The leakage power consumption may occur when the device is not operating and power continues to be consumed based on the leakage current which flows through the transistors, in the off state, that make up the electronic device.
Leakage current may include what is commonly referred to as “sub-threshold leakage” and “gate leakage.” Sub-threshold leakage may refer to the current that flows in the channel of the transistor when the transistor is deactivated, i.e., turned off. Sub-threshold leakage may have an exponential dependency on the threshold voltage divided by thermal energy (kT). Hence, as the threshold voltage is decreased, the sub-threshold leakage is increased.
“Gate leakage” current may refer to the tunneling of carriers across the gate oxide of a transistor. Gate leakage may be directly related to the size of the gate oxide. The thinner the gate oxide, the greater the gate leakage.
Leakage power consumption has become a major design concern for sub-micron transistors especially in low power applications, e.g., portable computers. For example, in portable computers with battery operation, leakage power consumption may shorten the life of the battery. Consequently, techniques have been developed to mitigate leakage power consumption such as during the power saving mode of operation commonly referred to as “sleep mode” or “sleep state.”
Traditionally, mitigation techniques have focused only on the sub-threshold component of the leakage current as gate leakage has traditionally been an insignificant component of the total leakage current. However, gate leakage has been increasing as the gate oxide in transistors has been made increasingly thinner thereby causing gate leakage to become a significant fraction of the total leakage current.
An idea to mitigate gate leakage has been proposed in a paper entitled “Circuit Level Techniques to Control Gate Leakage for sub-100 nm CMOS” by Fatih Hamzaoglu, et al. The proposed idea was to use more P-channel Metal Oxide Semiconductor (PMOS) transistors than N-channel Metal Oxide Semiconductor (NMOS) transistors since PMOS gate leakage is lower than NMOS gate leakage. However, this results in significant performance degradation.
Therefore, there is a need in the art to minimize transistor gate leakage without adversely effecting performance such as during the sleep state.
SUMMARY
The problems outlined above may at least in part be solved in some embodiments by producing substantially identical voltages at the source, gate and drain terminals of a majority of the transistors in a circuit during a sleep state.
In one embodiment of the present invention, a method for mitigating transistor gate leakage during a sleep state may comprise the step of applying an input pattern to one or more of a plurality of devices in a circuit during the sleep state. A substantially identical voltage may be produced at the source, gate and drain terminals of a majority of the devices in the circuit as a result of applying the input pattern thereby mitigating gate leakage.
The foregoing has outlined rather broadly the features and technical advantages of one or more embodiments of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.


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Faith Hamzaoglu et al. “Circuit-Level Techniques to Control Gate Leakage for sub-100nm CMOS,” High-Performance Low-Power (HPLP) Lab, ECE Department, University of Virginia, pp. 60-63, Aug. 2002.

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