Techniques for reducing clock skew in clock routing networks

Details Techniques for reducing clock skew in clock routing networks Techniques for reducing clock skew in clock routing networks

2008-03-22

2009-12-29

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S041000

Reexamination Certificate

active

07639047

ABSTRACT:
A circuit includes a clock routing network. The clock routing network includes first and second clock paths. The first clock path routes a first clock signal to sub-circuits in the circuit. The first clock path has first buffers that buffer the first clock signal at the sub-circuits and first conductors in a first conductive layer of the circuit that transmit the first clock signal. The second clock path routes a second clock signal to the sub-circuits. The second clock path has second buffers that buffer the second clock signal at the sub-circuits, second conductors in the first conductive layer that transmit the second clock signal, and third conductors in a second conductive layer of the circuit. The second clock signal is routed through the third conductors at overlaps between the first clock path and the second clock path.

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