Two-phase overlapping clocking technique for digital dynamic cir

Details Two-phase overlapping clocking technique for digital dynamic cir Two-phase overlapping clocking technique for digital dynamic cir

1994-08-19

1996-04-02

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 96, 377 78, H03K 1900

Patent

active

055044417

ABSTRACT:
A digital dynamic circuit is presented which effectively extends the percentage of each clock cycle available for logical operations. The circuit uses a two-phase overlapping clocking design which results in the circuit (1) having only a single latch delay, (2) being insensitive to mid-cycle clock jitter, and (3) being insensitive to the discrete nature of gate delays. Thus, the circuit can better utilize the time available to perform logic.

REFERENCES:
patent: 4687959 (1987-08-01), Eitrheim
patent: 4745302 (1988-05-01), Hanawa
patent: 4852061 (1989-07-01), Baron
patent: 5003201 (1991-03-01), Bai
patent: 5023484 (1991-06-01), Pathak et al.
patent: 5289050 (1994-02-01), Ogasawara
patent: 5321368 (1994-06-01), Hoelze

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