System level hardening of asynchronous combinational logic

Details System level hardening of asynchronous combinational logic System level hardening of asynchronous combinational logic

2003-12-09

2004-09-14

Le, Don (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S014000, C326S038000

Reexamination Certificate

active

06791362

ABSTRACT:

FIELD
The present invention relates generally to asynchronous logic circuits, and more particularly, relates to system level hardening of asynchronous combinational logic circuits.
BACKGROUND
Most digital circuits are synchronous in nature, meaning that a clock signal controls data flow through the circuit. As clock speeds increase, circuit design becomes more complex due to timing requirements. Problems related to high clock speeds include switching noise, peak currents on power rails, and unnecessary power consumption due to the switching noise. As a result of the problems encountered with synchronous circuit design, asynchronous design techniques have received more attention.
One such asynchronous approach is null convention logic (NCL). NCL is a clock-free delay-insensitive logic design methodology for digital systems. NCL uses a combination of multi-wire data representation and a control/signaling protocol. NCL circuits switch between a data representation of DATA and a control representation of NULL. Typically, DATA corresponds to a logic-1 level, while NULL corresponds to a logic-0 level. The separation between data and control representations provides self-synchronization, without the use of a clock signal.
The use of asynchronous circuit designs, such as NCL, may be advantageous in space, weapons, and aviation applications. However, these applications expose circuits to radiation. Radiation may take the form of alpha and energetic particles, as well as in other forms, such as gamma rays. Alpha particles are byproducts of the natural decay of elements. Energetic particles include heavy ions, protons, neutrons, and electrons, which are abundant in space, even at commercial flight altitudes.
Radiation can cause transient disturbances, or glitches, in asynchronous circuit designs. When an energetic particle strikes a transistor region, a parasitic conduction path can be created, which may cause a false transition. The false transition, or glitch, can propagate through the circuit and may ultimately result in the disturbance of a state node containing state information, such as an output of a latch, register, or gate. The disturbance of the state node is commonly referred to as a single event upset (SEU). SEU is a specific class of transient fault. Other sources of transient faults exist and may have similar effects.
The circuit implementation of the basic NCL building block gate uses a latch element that is sensitive to upset due to transient disturbances caused by radiation. Many of these gates may be used in the design of asynchronous combinational logic circuits. Therefore, it would be beneficial to harden an asynchronous combinational logic circuit from the effects of SEU. As a result of hardening, asynchronous combinational logic circuits may be used in applications in which radiation is present.


REFERENCES:
patent: 3783254 (1974-01-01), Eichelberger
patent: 4782467 (1988-11-01), Belt et al.
patent: 4805148 (1989-02-01), Diehl-Nagle et al.
patent: 5305463 (1994-04-01), Fant et al.
patent: 5387825 (1995-02-01), Cantrell et al.
patent: 5406513 (1995-04-01), Canaris et al.
patent: 5640105 (1997-06-01), Sobelman et al.
patent: 5652902 (1997-07-01), Fant
patent: 5656948 (1997-08-01), Sobelman et al.
patent: 5664211 (1997-09-01), Sobelman et al.
patent: 5664212 (1997-09-01), Fant et al.
patent: 5764081 (1998-06-01), Fant et al.
patent: 5793662 (1998-08-01), Duncan et al.
patent: 5796962 (1998-08-01), Fant et al.
patent: 5828228 (1998-10-01), Fant et al.
patent: 5896541 (1999-04-01), Fant et al.
patent: 5907693 (1999-05-01), Fant et al.
patent: 5923194 (1999-07-01), Graf, III
patent: 5930522 (1999-07-01), Fant
patent: 5977663 (1999-11-01), Fant et al.
patent: 5986466 (1999-11-01), Sobelman et al.
patent: 6020754 (2000-02-01), Sobelman et al.
patent: 6031390 (2000-02-01), Fant et al.
patent: 6043674 (2000-03-01), Sobelman
patent: 6052770 (2000-04-01), Fant
patent: 6128678 (2000-10-01), Masteller
patent: 6262593 (2001-07-01), Sobelman et al.
patent: 6278287 (2001-08-01), Baze
patent: 6292128 (2001-09-01), Tsui et al.
patent: 6308229 (2001-10-01), Masteller
patent: 6313660 (2001-11-01), Sobelman et al.
patent: 6326809 (2001-12-01), Gambles et al.
patent: 6327607 (2001-12-01), Fant
patent: 6333640 (2001-12-01), Fant et al.
patent: 6356117 (2002-03-01), Sutherland et al.
patent: 6526542 (2003-02-01), Kondratyev
patent: 6586969 (2003-07-01), Koe
patent: 6700410 (2004-03-01), Ebergen
patent: 2003/0091038 (2003-05-01), Hagedorn
Maher, Michael, “Radiation Design Considerations Using CMOS Logic,” National Semiconductor Application Note 926, Jan. 1994.
“Throw Away the Clock,” Theseus Logic—Benefits of NCL—EMI, http://www.theseus.com/_AboutNCL.htm, printed Nov. 19, 2002.
Fant, Karl M. and Scott A. Brandt, “NULL Convention Logic,” Theseus Logic: Setting the Standard for Clockless Systems, 1997.

Affiliated with

Also associated with

Rating

System level hardening of asynchronous combinational logic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System level hardening of asynchronous combinational logic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System level hardening of asynchronous combinational logic will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3209161