Systems and methods for A 5:1 multiplexer with a one-fifth...

Details Systems and methods for A 5:1 multiplexer with a one-fifth... Systems and methods for A 5:1 multiplexer with a one-fifth...

2007-01-11

2008-09-09

Chang, Daniel D (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S038000, C327S407000

Reexamination Certificate

active

07423455

ABSTRACT:
The present invention provides methods and systems for multiplexing five channels, such as 10 Gb/s to 50 Gb/s, into a single data sequence using a 5:1 multiplexer using a ⅕thratio duty cycle clock. The ⅕thratio duty cycle clock is a clock with a period equal to the channel data rate, and a pulse width equal to the period of data rate five times higher. The ⅕thratio duty clock is combined with a proper combination of delays and phase shifters to allow the use of AND gates and OR gates to combine the five channels in a proper sequence to create a serial five-times higher data sequence.

REFERENCES:
patent: 7325024 (2008-01-01), Mathew et al.
Charles C. Lin; “Case Study: Implementing a 5-1 MUX”; 2003, All rights reserved.

Affiliated with

Also associated with

Rating

Systems and methods for A 5:1 multiplexer with a one-fifth... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Systems and methods for A 5:1 multiplexer with a one-fifth..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systems and methods for A 5:1 multiplexer with a one-fifth... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3988672