Transfer of digital data across asynchronous clock domains

Details Transfer of digital data across asynchronous clock domains Transfer of digital data across asynchronous clock domains

2005-05-31

2005-05-31

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Metastable state prevention

C375S354000, C327S145000

Reexamination Certificate

active

06900665

ABSTRACT:
A method and circuit for transferring multiple bits of data across asynchronous clock domains is provided. The method includes detecting a change in a status bit of a data word being transferred from a source in a source clock domain to a destination register in a destination clock domain, the source clock and destination clock being asynchronous. The method includes sampling the detected change in reference to a change window where the change window is sized to encompass all bits of the data word. A stable input is selected for each bistable circuit of the destination register based on whether the detected change in the status bit is likely to produce metastability in the receiving register.

REFERENCES:
patent: 5602878 (1997-02-01), Cross
patent: 6055285 (2000-04-01), Alston
ICT paper entitled “PEEL™ Device Metastability”; date unknown but known to be before Jun. 10, 2003; 3 pp.
Semiat, et al., “Timing Measurements of Synchronization Circuits,” VLSI Systems Research Center, Technion—Israel Institute of Technology, Haifa, Israel; May 2003; 10 pp.
Varma, et al., “Metastability Reduction by Aperture Transformation,” IBM India Research Laboratory, Centre for Applied Research Electronics, New Delhi, India; date unknown but known to be before Jun. 10, 2003; 10pp.

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