Teacher-pupil flip-flop

Details Teacher-pupil flip-flop Teacher-pupil flip-flop

2005-10-18

2005-10-18

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S046000, C327S199000, C327S212000

Reexamination Certificate

active

06956405

ABSTRACT:
A teacher-pupil flip-flop with reduced register delay including a gate circuit, a stack circuit, a keeper circuit, a teacher output circuit, a latch circuit and a pupil output circuit. The gate circuit switches after a setup delay in response to transitions of a clock signal. The stack circuit, coupled to the gate circuit output and to an input, switches an intermediate node pair to a preliminary state when the clock signal is low, and to a data state indicative of the input after the setup delay when the clock signal goes high. The keeper circuit maintains the data state and the teacher output circuit drives the output based on the data state while the clock is high. The latch circuit stores the data state and the pupil output circuit drives the output with valid data from the latch circuit after the clock signal goes low.

REFERENCES:
patent: 5656962 (1997-08-01), Banik
patent: 6097230 (2000-08-01), Bareither
patent: 6566927 (2003-05-01), Park et al.
patent: 6573775 (2003-06-01), Pilling
patent: 6577176 (2003-06-01), Masleid et al.

Affiliated with

Also associated with

Rating

Teacher-pupil flip-flop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Teacher-pupil flip-flop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Teacher-pupil flip-flop will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3486547