Time multiplexed ratioed logic

Details Time multiplexed ratioed logic Time multiplexed ratioed logic

1994-08-17

1997-03-18

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326121, 326122, H03K 19096, H03K 19094

Patent

active

056126387

ABSTRACT:
A robust family of pre-conditioned complementary CMOS logic elements using scaled MOSFETs and a single clock phase which may be easily interconnected to form high speed logic networks. The family includes both N-type and P-type pre-conditioned logic elements using a skewed complementary CMOS structure to achieve low power and high speed. The logic elements achieve next generation CMOS performance yet are manufactured using present day processes and equipment. Logic element implementation is described in detail. A method for scaling the MOSFETs according to the present invention is provided, and several routing methods for reducing interconnection cross-talk are set forth.

REFERENCES:
patent: 3737673 (1973-06-01), Suzuki
patent: 4682055 (1987-07-01), Upadhyayula
patent: 4851714 (1989-07-01), Hwang
"Analysis And Design Of Digital Integrated Circuits", Hodges et al, McGraw-Hill, 1983, pp. 98-102.
Shoji, Masakazu, CMOS Digital Circuit Technology, 1988, pp. 61, 210-243, 349 and 377-381, Prentic Hall, Englewood Cliffs, NJ.

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