Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2006-11-28
2009-12-15
Cho, James (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S033000
Reexamination Certificate
active
07633314
ABSTRACT:
System and method for reducing power-on transient current magnitude on distributed header switches. A preferred embodiment comprises a distributed header switch coupling a circuit to a power supply, the distributed header switch comprising a linear sequence of combination switches, each combination switches containing a pre-charge switch and a header switch. A first-pass involves sequentially turning on each of the pre-charge switches, which enables a voltage level at the distributed header switch to approach that of a final voltage level and a second-pass involves sequentially turning on each of the header switches. Since the voltage level at the distributed header switches is close to the final voltage level, a resulting transient current is small in magnitude.
REFERENCES:
patent: 5926430 (1999-07-01), Noda et al.
patent: 6433614 (2002-08-01), You et al.
patent: 6836179 (2004-12-01), Mizuno et al.
patent: 6946901 (2005-09-01), Kang et al.
Lagerquist Rolf
Mair Hugh
Brady III Wade James
Cho James
Neerings Ronald O.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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