High-speed data transfer synchronizing system and method
Independent timing compensation of write data path and read data
Input circuit and method for the operation thereof
Input signal phase compensation circuit capable of reliably obta
Integrated circuit I/O using a high performance bus interface
Interleaved delay line for phase locked and delay locked loops
Interleaved delay line for phase locked and delay locked loops
Interleaved delay line for phase locked and delay locked loops
Intra-pair differential skew compensation method and...
Latency adjustment between integrated circuit chips
Measure controlled delay with duty cycle control
Memory controller and signal synchronizing method thereof
Memory controller driver circuitry having a multiplexing...
Memory device controls delay time of data input buffer in...
Memory system and data transmission method
Memory system and data transmission method
Memory system using complementary delay elements to reduce...
Memory system, module and register
Method and an apparatus for adjusting clock signal to sample...
Method and apparatus for adjusting data hold timing of an...