Latency adjustment between integrated circuit chips

Details Latency adjustment between integrated circuit chips Latency adjustment between integrated circuit chips

2006-10-27

2010-10-26

Stoynov, Stefan (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S502000, C713S503000, C713S600000, C702S176000, C703S013000, C703S023000, C327S158000, C327S161000, C375S358000, C375S368000

Reexamination Certificate

active

07823001

ABSTRACT:
In emulation systems having a plurality of chips, data communicated between the chips needs to be synchronized. A receiver chip may push or pull on incoming data from an emitter chip in order to synchronize it with a receiver clock. Unexpected latency on the link between the emitter and receiver chips may also be adjusted for.

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Data to Clock Phase Alignment, Nick Sawyer, Xilinx Application Note, Apr. 4, 2002.

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