Memory controller and signal synchronizing method thereof

Details Memory controller and signal synchronizing method thereof Memory controller and signal synchronizing method thereof

2011-02-15

2011-02-15

Butler, Dennis M (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S501000, C713S503000

Reexamination Certificate

active

07890786

ABSTRACT:
A memory controller includes an output buffer for receiving a clock signal and outputting the clock signal to an external memory; and a replica buffer for receiving the clock signal and outputting the clock signal to a counting circuit; wherein the replica buffer and the output buffer have the same delay time such that the clock signal received by the counting circuit can be synchronized with that received by the external memory, and therefore the counting circuit can accurately count to a predetermined time according to the clock signal and output an enabling signal to enable a data control signal. The present invention further provides a signal synchronizing method for the memory controller.

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patent: 20040046328 (2004-06-01), None
patent: 591658 (2004-06-01), None

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