Capture clock generator using master and slave delay locked...
Circuit arrangement
Circuit arrangement
Circuit for aligning signal with reference signal
Circuit in which the time delay of an input clock signal is...
Circuit interface synchronization using slave variable delay loo
Circuitry, architecture and method(s) for synchronizing data
Clock and data signal separator circuit
Clock circuit and a computer system having said clock circuit
Clock controller for controlling the switching to redundant...
Clock data recovery (CDR) system using interpolator and...
Clock distribution without clock delay or skew
Clock distributor for use in semiconductor logics for...
Clock generating apparatus for skew control between two-phase no
Clock skew reduction technique based on distributed process...
Clock synchronization of multiprocessor systems
Clocking an I/O buffer, having a selectable phase difference...
Clocking architecture to compensate a delay introduced by a...
Computer system having memory device with adjustable data...
Computer system having memory device with adjustable data...