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Independent timing compensation of write data path and read data

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Patent

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Input circuit and method for the operation thereof

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate

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Input signal phase compensation circuit capable of reliably obta

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Patent

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Integrated circuit I/O using a high performance bus interface

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
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Interleaved delay line for phase locked and delay locked loops

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
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Interleaved delay line for phase locked and delay locked loops

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
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Interleaved delay line for phase locked and delay locked loops

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate

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Intra-pair differential skew compensation method and...

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
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