Adjustable byte lane offset for memory module to reduce skew

Details Adjustable byte lane offset for memory module to reduce skew Adjustable byte lane offset for memory module to reduce skew

2005-05-09

2008-11-25

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S400000, C711S100000

Reexamination Certificate

active

07457978

ABSTRACT:
Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for such skew, an on-chip delay is added to the data out paths of those bits in the byte lane with otherwise would arrive early to their destinations. Such on-chip delay is provided delay circuits preferably positioned directly before the output buffers/bond pads of the integrated circuit or module. By intentionally delaying some of the outputs from the integrated circuit or module, external skew is compensated for so that all data in the byte lane arrives at the destination at substantially the same time. In a preferred embodiment, the delay circuits are programmable to allow the integrated circuit or module to be freely tailored to environments having different skew considerations, such as different styles of connectors.

REFERENCES:
patent: 5406518 (1995-04-01), Sun et al.
patent: 5703815 (1997-12-01), Kuhara et al.
patent: 5727021 (1998-03-01), Truebenbach
patent: 5946712 (1999-08-01), Lu et al.
patent: 6031847 (2000-02-01), Collins et al.
patent: 6150863 (2000-11-01), Conn et al.
patent: 6464540 (2002-10-01), Sato
patent: 6484299 (2002-11-01), Larsen
patent: 6629222 (2003-09-01), Jeddeloh
patent: 6708238 (2004-03-01), Rotker
patent: 6763444 (2004-07-01), Thomann et al.
patent: 6832277 (2004-12-01), Durham et al.
patent: 6889336 (2005-05-01), Schoenfeld et al.
patent: 6963989 (2005-11-01), Cullum et al.
patent: 6968436 (2005-11-01), Kumazawa
patent: 6971040 (2005-11-01), Volk
patent: 6998892 (2006-02-01), Nguyen et al.
patent: 7039822 (2006-05-01), Faue et al.
patent: 7051225 (2006-05-01), Nishio et al.
patent: 7079446 (2006-07-01), Murtagh et al.
patent: 7110276 (2006-09-01), Park
patent: 7193910 (2007-03-01), Nobunaga et al.
patent: 7281950 (2007-10-01), Belopolsky
patent: 2002/0091958 (2002-07-01), Schoenfeld et al.
patent: 2002/0174313 (2002-11-01), Kuhn
patent: 2002/0181214 (2002-12-01), Levy et al.
patent: 2002/0199126 (2002-12-01), Volk
patent: 2003/0046618 (2003-03-01), Collins
patent: 2003/0112827 (2003-06-01), Cox et al.
patent: 2005/0005184 (2005-01-01), Lindt
patent: 2005/0047187 (2005-03-01), Park
patent: 2005/0057978 (2005-03-01), Stubbs
patent: 2005/0226061 (2005-10-01), Park

Affiliated with

Also associated with

Rating

Adjustable byte lane offset for memory module to reduce skew does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Adjustable byte lane offset for memory module to reduce skew, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Adjustable byte lane offset for memory module to reduce skew will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4039907