Apparatus and method for asynchronously interfacing...

Details Apparatus and method for asynchronously interfacing... Apparatus and method for asynchronously interfacing...

2005-08-16

2005-08-16

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S500000, C713S501000, C713S600000, C327S145000

Reexamination Certificate

active

06931561

ABSTRACT:
Interfacing circuitry for asynchronously transferring data between a high-speed clock domain and a low-speed clock domain is provided. The interfacing circuitry is divided into halves, with one half being synchronized to a first clock and the second half being synchronized to a second clock. The first half and the second half are mirror images of each other. Each half has at least one storage component, such as a register and a flip-flop, for storing a valid bit as well as data, and at least one multiplexer component for gating the storage component. The valid bit is used to control the multiplexer at a receiving half. When transferring from a high-speed clock domain to a low-speed clock domain, the high-speed clock domain may probe the received data and/or the valid bit stored in the low-speed clock domain before the high-speed clock domain sends additional data.

REFERENCES:
patent: 5434996 (1995-07-01), Bell
patent: 6131173 (2000-10-01), Meirlevede et al.
patent: 6255869 (2001-07-01), Fischer
patent: 6389567 (2002-05-01), Porteners et al.
Meirlevede et al., PCT/IB97/01346, Jun. 18, 1998.

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