Adaptive data processing scheme based on delay forecast

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

Reexamination Certificate

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C713S502000, C710S058000

Reexamination Certificate

active

10527853

ABSTRACT:
The present invention relates to a data processing circuitry and method of processing an input data pattern and out-putting an output data pattern after a processing delay which depends on a processing activity of the data processing circuitry, wherein the processing delay is estimated based on the input pattern and the processing is controlled in response to the estimated processing delay. The processing control may be a power control based on an activity monitoring or a clock control in a pipeline structure. Thereby, an efficient solution is provided to derive the current activity of the processing circuitry in order to dynamically adapt its operating conditions to its demands.

REFERENCES:
patent: 6522706 (2003-02-01), Bahai et al.
patent: 6807500 (2004-10-01), Johnson et al.
patent: 7036037 (2006-04-01), Paul et al.
patent: WO 9950722 (1999-10-01), None
patent: WO 0178423 (2001-10-01), None

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