1000 mb phase picker clock recovery architecture using interleav

Details 1000 mb phase picker clock recovery architecture using interleav 1000 mb phase picker clock recovery architecture using interleav

1998-05-18

2000-03-07

Butler, Dennis M.

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

713503, 713600, G06F 112

Patent

active

060354097

ABSTRACT:
A clock recovery architecture for recovering clock and serial data from an incoming data stream provided by a node of a local area network. A phase picker architecture augmented by a phase interpolator is used as part of the clock recovery architecture to enhance phase resolution. The present invention uses interleaved phase detectors to recover a 125 mhz clock and 10 bit rxd vector from a 1000 mb (1.25 Ghz embedded clock) serial input data stream. The inventive architecture can be used to recover clock and data from any high frequency data stream (provided that embedded clock is such that a narrow band CRM suffices), using a low frequency CGM to provide multiple clock phases for CRM.

REFERENCES:
patent: 5374860 (1994-12-01), Llewellyn
patent: 5754835 (1998-05-01), Lin et al.
patent: 5802103 (1998-09-01), Jeong
patent: 5864250 (1999-01-01), Deng
patent: 5945860 (1999-08-01), Guay et al.

Affiliated with

Also associated with

Rating

1000 mb phase picker clock recovery architecture using interleav does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with 1000 mb phase picker clock recovery architecture using interleav, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and 1000 mb phase picker clock recovery architecture using interleav will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-373240