Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
1999-07-29
2002-10-15
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S400000, C713S500000
Reexamination Certificate
active
06467043
ABSTRACT:
BACKGROUND
The invention relates to adjusting the timing of a data strobe signal.
Referring to
FIG. 1
, delay elements, such as inverters
4
and
6
, may be used for purposes of purposes of delaying a signal (called IN) to produce another signal (called OUT). Such delays may be desirable in the capture of data from a bus. For example, a memory controller may use a data strobe signal called DQS (see
FIG. 4
) of a double data rate (DDR) memory bus to synchronize the capture of data from the bus. However, before the data is captured, the memory controller may need to shift the DQS signal in time for purposes of aligning the DQS signal with signals (an exemplary signal called DQ for a bit of data is depicted in
FIG. 6
) of the bus that indicate the data.
In this manner, the DQS signal may be used by a memory controller, for example, during a burst memory read operation (depicted in
FIGS. 2
,
3
,
4
and
6
) that occurs over the memory bus. In the read operation, a memory device (a DDR synchronous dynamic random access memory (SDRAM), for example) furnishes signals that indicate the data and furnishes the DQS signal to synchronize the capture of the data by the memory controller. More specifically, the burst read operation may begin near time T
0
when the memory controller furnishes signals (to the memory bus) that indicate a read command, as depicted in FIG.
3
. In response to the read command, the memory device may begin furnishing the DQS signal at time T
1
by driving the DQS signal from a tri-stated level to a logic zero level. From times T
2
to T
4
, the memory device drives the DQS signal in synchronization with a clock signal called CK (see
FIG. 2
) that is fumished by the memory controller. On each positive and negative edge of the DQS signal, the memory device begins furnishing a different set of signals (to the data lines of the memory bus), each of which indicates a different set of data.
The memory controller may use the edges of the DQS signal to trigger the capture of each set of data from the memory bus. However, due to the finite rise and fall times that are introduced by the memory bus, each data signal may have a narrow window in which the signal accurately indicates its bit of data. This narrow window typically is called a data eye and represents the time interval in which the bit of data (as indicated by the corresponding data signal) is valid. For example, for a particular bit (bit D
0
) of data (represented by a portion of a signal called DQ (see FIG.
6
)), the data eye may occur around time T
3
, a time approximately near the center of the window in which the DQ signal indicates the D
0
bit of data. Thus, because the memory controller may use the edges of the DQS signal to capture the data, the memory controller has to shift DQS signal in time to produce a delayed internal data strobe signal (called DQS
2
and depicted in
FIG. 5
) so that the strobe edges of the DQS
2
signal are aligned with the data eyes. Therefore, as an example, the first positive edge of the DQS
2
signal is approximately centered in the data eye of the first set of data signals.
Unfortunately, the propagation delay that the memory controller introduces to the DQS signal to produce the DQS
2
signal may vary with temperature and voltages of the computer system, i.e., parameters that tend to fluctuate during operation of the computer system. This variation of the propagation delay may cause the strobe edges of the DQS
2
signal to occur outside of the data eyes, a misalignment that may cause memory read errors.
Thus, there is a continuing need for an arrangement that addresses one or more of the above-stated problems stated above.
SUMMARY
In one embodiment of the invention, a method for use with a computer system includes receiving a first data strobe signal from a bus and introducing a delay to the first data strobe signal to produce a second data strobe signal. The method includes determining whether the delay is within a predetermined range of delays, and if not, the method includes adjusting the delay to cause the delay to be within the predetermined range. The second data strobe signal is used to capture data from the bus.
In another embodiment, a bridge includes a delay circuit and a memory interface. The delay circuit is adapted to receive a first data strobe signal from a bus, introduce a first delay to the first data strobe signal to produce a second data strobe signal, indicate whether the first delay is within a predetermined range of delays, and if not, adjust the first delay to be within the predetermined range. The memory interface is adapted to use the use the second data strobe signal to capture data from the bus.
Advantages and other features of the invention will become apparent from the following description, from the drawing and from the claims.
REFERENCES:
patent: 5848109 (1998-12-01), Marbot et al.
patent: 5948083 (1999-09-01), Gervasi
patent: 6101612 (2000-08-01), Jeddeloh
Gaffin Jeffrey
Micro)n Technology, Inc.
Peyton Tammara
Trop Pruner & Hu P.C.
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