Adaptive clock skew in a variably loaded memory bus

Details Adaptive clock skew in a variably loaded memory bus Adaptive clock skew in a variably loaded memory bus

2006-03-21

2006-03-21

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S400000, C713S500000, C713S503000, C365S233100

Reexamination Certificate

active

07017068

ABSTRACT:
The preferred embodiments of the present invention are directed to the selective phase lag and time delay of clock signals within a computer system to compensate for additional parasitic capacitance that may be added to that system because of its open architecture. More particularly, the preferred embodiments are directed to clock signal path circuits where each circuit has multiple signal paths of varying lengths. By allowing the clock signals to propagate along a particular path, phase lag or time delay is added to those clock signals. Selection of a particular path for the clock signal is made by activating electrically controlled switches which themselves are activated or deactivated by software programs that run during power-up of the computer system that determine required phase lag or time delay of those clock signals as a function of parasitic capacitance in the computer system.

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Neil H. E. Weste and Kamran Eshraghian, “Principles of CMOS VLSI Design,” Addison-Wesley Publishing Company, Second Edition, Page(s) 17-18.

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