Adjustable data delay using programmable clock shift

Details Adjustable data delay using programmable clock shift Adjustable data delay using programmable clock shift

1999-04-23

2003-09-30

Butler, Dennis M. (Department: 2185)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S503000

Reexamination Certificate

active

06629250

ABSTRACT:

TECHNICAL FIELD
This invention is in the field of data transmission circuits and more particularly is directed towards a data transmission circuit that ensures accurate timing of transmitted signals on transmission lines having different lengths and propagation speeds.
BACKGROUND OF THE INVENTION
Data is transferred from one circuit to another on a transmission line. The length of the transmission line is often determined by the distance between the two circuits. The time between when the data is sent by the first circuit until the data is received by the second circuit is largely a function of the length of the transmission line.
If the clock speed of the system is increased, the real time required for data to travel on a transmission line does not charge, but the relative time changes. A data signal that formerly traveled down a transmission line in two clock cycles will now require three clock cycles if the clock speed is increased by about 30%. In the prior art, one solution is to never change the clock speed of the system. However, this limits system modification and performance enhancement at a later time. It also makes it difficult to test the system at different clock speeds.
It is also often desirable to ensure that the relative timing between many signals traveling on different transmission lines is kept the same when the data is transmitted from one circuit to a second circuit. If all transmission lines are the same length, or nearly the same length as each other, then maintaining the same relative timing is quite easy. However, there are a number of applications in which the difference in length between the transmission lines are sufficiently great that a timing skew occurs between data sent on two different transmission lines having different lengths from each other. If this timing skew becomes sufficiently great, the reliability of the data on the first transmission lines relative to each other can no longer be assured, and subsequent problems may result.
One current solution to avoid the skew when transmitting data from one circuit to the other is to ensure that all data transmission lines have approximately the same length as each other. Accordingly, when one line is significantly shorter than other lines, its length is increased by routing it in a different pattern between the two circuits It may, for example, undergo a number of bends and turns, some of them being 90 degree turns tightly positioned one after the other in order to achieve the desired length. Such a solution has the disadvantage of requiring that all transmission lines be the same physical length as the longest transmission line. All data transmission therefore is slowed based on the slowest possible communication link between the two circuits. This also has the disadvantage of consuming significant area between the two circuits. If the circuits are on an integrated chip, adding length to the transmission lines will consume already precious chip area. It may also add undesired capacitance or, in some cases, inductance, to the lines depending upon the layout and shape of the delay patterns.
SUMMARY OF THE INVENTION
According to principles of the present invention, a circuit is provided for permitting the clock speed of a system to be changed by a large amount and still ensure accurate operation of the whole system. The circuit also provides for electronically matching and synchronizing the receipt of data on transmission lines of various lengths between two circuits.
A sending circuit and a receiving circuit are connected to each other to exchange signals. A transmission line between the sending circuit and the receiving circuit carries signals in the form of data. The receiving circuit includes a master latch which receives the data sent on the transmission line. The timing for control of the output of the master latch is controlled by a first clock signal. A slave latch receives the output from the master latch. The timing of the output from the slave latch is controlled by a second clock signal which is different from the first clock signal. A variable delay circuit is connected to the clock signal for the master latch. The variable delay circuit includes a plurality of delay elements. A selected number of delay elements are positioned in the path of the clock for the master latch. The number of delay elements selected is under software control so that the delay is programmable. Different delays may be programmed depending on the clock frequency, the transmission line length, the speed at which the data is being sent, the types of circuits or other factors.
According to one embodiment, the software is scanned into a select register for storage when the circuit is initialized. The output of the select register controls a multiplexer for selecting one line output from a number of inputs. A number of delay lines, each having different amounts of delay are coupled as inputs to the multiplexer. That delay line providing the appropriate delay is selected as the output for delaying the clock to the master latch.
The clocks of the master latch and the slave latch for each transmission line or each set of transmission lines are controlled to ensure that the data output of the slave latch is always synchronized with the data output from the slave latch on other transmission lines between the two circuits. The amount of delay is programmable on each transmission line in the receiving circuit. Therefore, the timing for receiving the data at each of the input terminals of the second circuit can be controlled to ensure they have the same relation to each other as they had when the sending circuit transmitted the data.
Having the amount of delay software programmable provides the further advantage that the amount of delay can be easily customized in the receiving circuit after the transmission lines are created and can be changed whenever desired. It may be desired at various times to change the amount of delay on the transmission lines even though their length relative to one another remains the same. For example, the clock frequency may be increased, or each transmission line may behave differently when data is transmitted at a slow rate, such as 50 megahertz, as compared to when data is transmitted at a fast rate, such as 500 megahertz or higher. Accordingly, according to the present invention, the relative delay on one set of transmission lines or between the transmission lines can be reprogrammed based on the different transmission frequencies or any other factor.


REFERENCES:
patent: 4584695 (1986-04-01), Wong et al.
patent: 4821297 (1989-04-01), Bergmann et al.
patent: 4943984 (1990-07-01), Pechanek et al.
patent: 4965884 (1990-10-01), Okura et al.
patent: 5615358 (1997-03-01), Vogley
patent: 5670904 (1997-09-01), Moloney et al.
patent: 5778214 (1998-07-01), Taya et al.
patent: 5926838 (1999-07-01), Jeddeloh
patent: 5987619 (1999-11-01), Hamamoto et al.
patent: 6128748 (2000-10-01), MacWilliams et al.
Gail Alverson et al., “Tera Hardware-Software Corporation”, inProceedings of Supercomputing, Nov. 1997.
Gail Alverson et al., “Scheduling on the Tera MTA” inJob Scheduling Strategies for Parallel Processing, 949:of Lecture Notes in Computer Science, Springer-Verlag, 1995.
Robert Alverson et al., “The Tera Computer System”, inProceedings of 1990 ACM International Conference on Supercomputing, pp. 1-6, Jun. 1990.
D.H. Bailey et al., “The NAS Parallel Benchmarks—Summary and Preliminary Results”, inProceeding of Supercomputing '91, pp. 158-165, Nov. 1991.
David Callahan, Recognizing and Parallelizing Bounded Recurrences, inLanguages and Compilers for Parallel Computing, 589:of Lecture Notes in Computer Science, pp. 169-185, Springer-Verlag, 1992.
David Callahan et al., “Improving Register Allocation for Subscripted Variables”, inProceedings of the ACM SIGPLAN '90 Conference on Programming Language Design and Implementation, SIGPLAN Notices, 25(6):53-65, Jun. 1990.
David Callahan and Burton Smith, “A Future-based Parallel Language For a General-purpose Highly-parallel Computer”, inLanguages and C

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