Flow optimization and prediction for VSSE memory operations
Flow optimization and prediction for VSSE memory operations
Flushable free register list having selected pointers moving...
Forcing regularity into a CISC instruction set by padding...
Forwarding instruction byte blocks to parallel scanning...
Forwarding load data to younger instructions in annex
Forwarding store instruction result to load instruction with red
Forwarding stored dara fetched for out-of-order load/read...
Forwarding the results of operations to dependent...
Four stage pipeline processing for a microcontroller
FPGA based configurable CPU additionally including second progra
FPGA co-processor for accelerated computation
FPGA input output buffer with registered tristate enable
FPGA input output buffer with registered tristate enable
Function-variable type digital signal processing apparatus,...
Functional bit identifying a prefix byte via a particular state
Functional-level instruction-set computer architecture for...
Functional-level instruction-set computer architecture for...
Fusing load and alu operations
Fusing load and alu operations