Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
Patent
1997-04-10
2000-02-01
Kim, Kenneth S.
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
712218, 712225, G06F 934
Patent
active
060214856
ABSTRACT:
In a superscalar processor implementing out-of-order dispatching and execution of load and store instructions, when a store instruction has already been translated, the load address range of a load instruction is contained within the address range of the store instruction, and the data associated with the store instruction is available, then the data associated with the store instruction is forwarded to the load instruction so that the load instruction may continue execution without having to be stalled or flushed.
REFERENCES:
patent: 5606670 (1997-02-01), Abramson et al.
patent: 5659782 (1997-08-01), Senter et al.
patent: 5751946 (1998-05-01), Afsar et al.
patent: 5754812 (1998-05-01), Favor et al.
patent: 5784586 (1998-07-01), Simone et al.
Feiste Kurt Alan
Muhich John Stephen
Thatcher Larry Edward
White Steven Wayne
England Anthony V. S.
International Business Machines - Corporation
Kim Kenneth S.
Kordzik Kelly K.
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