Electrical computers and digital processing systems: processing – Instruction alignment
Reexamination Certificate
1999-02-02
2001-01-16
Kim, Kenneth S. (Department: 2783)
Electrical computers and digital processing systems: processing
Instruction alignment
C712S210000, C712S213000
Reexamination Certificate
active
06175909
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to scanning variable-length instructions within a microproccssor.
2. Description of the Relevant Art
The number of software applications written for the x86 instruction set is immense. As a result, despite the introduction of newer and more advanced instruction sets, microprocessor designers have continued to design microprocessors capable of executing the x86 instruction set.
The x86 instruction set is relatively complex and is characterized by a plurality of variable-length instructions. A generic format illustrative of the x86 instruction set is shown in FIG.
1
. As the figure illustrates, an x86 instruction consists of from one to five optional prefix bytes
102
, followed by an operation code (opcode) field
104
, an optional addressing mode (Mod R/M) byte
106
, an optional scale-index-base (SIB) byte
108
, an optional displacement field
110
, and an optional immediate data field
112
.
The opcode field
104
defines the basic operation for a particular instruction. The default operation of a particular opcode may be modified by one or more of the optional prefix bytes
102
. For example, one of prefix bytes
102
may be used to change the address or operand size for an instruction, to override the default segment used in memory addressing, or to instruct the processor to repeat a string operation a number of times. The opcode field
104
follows prefix bytes
102
, if present, and may be one or two bytes in length. The addressing mode (Mod R/M) byte
106
specifies the registers used as well as memory addressing modes. The scale-index-base (SIB) byte
108
is used only in 32-bit base-relative addressing using scale and index factors. A base field within SIB byte
108
specifies which register contains the base value for the address calculation, and an index field within SIB byte
108
specifies which register contains the index value. A scale field within SIB byte
108
specifies the power of two by which the index value will be multiplied before being added, along with any displacement, to the base value. The next instruction field is a displacement field
110
, which is optional and may be from one to four bytes in length. Displacement field
110
contains a constant used in address calculations. The optional immediate field
112
, which may also be from one to four bytes in length, contains a constant used as an instruction operand. The shortest x86 instructions are only one byte long, and comprise a single opcode byte. The 80286 sets a maximum length for an instruction at 10 bytes, while the 80386 and 80486 both allow instruction lengths of up to 15 bytes.
The complexity of the x86 instruction set poses many difficulties in implementing high performance x86-compatible microprocessors. In particular, the variable length of x86 instructions makes scanning, aligning, and decoding instructions difficult. Scanning refers to reading a group of instruction bytes (either from an instruction cache within the microprocessor or from an external memory) and determining the boundaries of instructions contained therein. Alignment refers to the process of masking off the undesired instruction bytes and shifting the desired instruction so that the first bit of the desired instruction is in the desired position. Decoding instructions typically involves identifying each field within a particular instruction, e.g., the opcode and operand fields. Decoding typically takes place after the instruction has been fetched from the instruction cache, scanned, and aligned.
One method for determining the boundaries of instructions involves generating a number of predecode bits for each instruction byte read from main memory. The predecode bits provide information about the instruction byte they are associated with. For example, an asserted predecode start bit indicates that the associated instruction byte is the first byte of an instruction. Similarly, an asserted predecode end bit indicates that the associated instruction byte is the last byte of an instruction. Once the predecode bits for a particular instruction byte are calculated, they are stored together with the instruction byte in an instruction cache. When a “fetch” is performed, i.e., a number of instruction bytes are read from the instruction cache, the associated start and end bits are also read. The start and end bits may then be used to generate valid masks for the individual instructions with the fetch. A valid mask is a series of bits in which each bit corresponds to a particular instruction byte. Valid mask bits associated with the first byte of an instruction, the last byte of the instruction, and all bytes in between the first and last bytes of the instruction are asserted. All other valid mask bits are not asserted.
Turning now to
FIG. 2
, an exemplary valid mask is shown. The figure illustrates a portion of a fetch block
120
and its associated start and end bits
122
and
124
. Assuming a valid mask
126
for instruction B
128
is to be generated, start and end bits
122
and
124
would be used to generate the mask. Valid mask
126
could then be used to mask off all bytes within fetch
120
that are not part of instruction B
128
. Once the boundaries of an instruction have been determined, alignment and decoding may be performed.
Unfortunately, the task of scanning x86 instructions typically requires a number of cascaded levels of logic. Thus, scanning may require a significant amount of time and, when added to the time required to perform alignment and decoding, may create a significant delay before any instructions are available to the functional stages of the microprocessor's pipeline. As microprocessors increase the number of instructions they are able to execute per clock cycle, slow instruction scanning may become a performance limiting factor. Therefore, a mechanism for simplifying the complexity and time required for instruction scanning is needed.
SUMMARY OF THE INVENTION
The problems outlined above may in part be solved by a microprocessor capable of using stored scanning history information. Broadly speaking, in one embodiment the microprocessor comprises: an instruction cache, a scanning history table, and two or more scanning units. The instruction cache may be configured to store instruction bytes received from a main system memory. The scanning history table may be configured to store scanning information indicative of where every “Nth” instruction begins in the instruction cache, wherein N is a predetermined integer greater than one. Once stored, the scanning information may be used to route instruction bytes that are fetched from the instruction cache to the scanning units. The stored scanning information may, in some embodiments, increase the number of instructions that may be scanned in a particular time period by allowing parallel scanning. In some embodiments, the stored scan information may also improve each scanning unit's ability to operate in parallel and independently from the other scanning unit(s). This may also reduce the possibility of one scanning unit stalling while waiting for portions of instructions from another scanning unit.
In one embodiment, the microprocessor may be configured to route requested fetch addresses to both the instruction cache and the scanning history table. When the instruction cache receives a fetch address, it may respond by outputting a plurality of corresponding sequential instruction bytes. The scanning history table may respond by outputting corresponding scanning information indicative of the start of the Nth instruction after the fetch address (i.e., scan block boundary information). The microprocessor may use the scanning information output by the scanning history table to route the first N instructions beginning at the fetch address to the first scanning unit. The second N instructions after the fetch address may be similarly routed to the second scanning.
In another embodiment, the microprocessor comprise two or more scanning units configured to operate in parall
Advanced Micro Devices , Inc.
Christen Dan R.
Conley Rose & Tayon PC
Kim Kenneth S.
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