Electrical computers and digital processing systems: processing – Instruction alignment
Patent
1998-04-30
2000-10-31
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Instruction alignment
712206, 712207, 712213, 712217, G06F 9312
Patent
active
061417459
ABSTRACT:
A superscalar microprocessor is provided that includes a predecode unit adapted for predecoding variable byte-length instructions. The predecode unit predecodes the instructions prior to their storage within an instruction cache. In one system, a predecode unit is configured to generate a plurality of predecode bits including a start bit, an end bit, and a functional bit for each instruction byte. The plurality of predecode bits associated with each instruction byte are collectively referred to as a predecode tag. An instruction alignment unit then uses the predecode tags to dispatch the variable byte-length instructions to a plurality of decode units within the superscalar microprocessor. The predecode unit is configured such that the meaning of the functional bit of a particular predecode tag is dependent upon the status of the end bit. The predecode unit is further configured to generate functional bits associated with bytes of an instruction other than the ending byte, which indicate whether the bytes of the instruction other than the ending byte is a prefix. The encoding of the predecode tags is such that a relatively large amount of predecode information may be conveyed with a relatively small number of predecode bits.
REFERENCES:
patent: 3585605 (1971-06-01), Gardner
patent: 4044338 (1977-08-01), Wolf
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4807115 (1989-02-01), Torng
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4928223 (1990-05-01), Dao et al.
patent: 5053631 (1991-10-01), Perlman et al.
patent: 5058048 (1991-10-01), Gupta et al.
patent: 5129067 (1992-07-01), Johnson
patent: 5136697 (1992-08-01), Johnson
patent: 5179674 (1993-01-01), Williams et al.
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5337415 (1994-08-01), DeLano et al.
patent: 5357618 (1994-10-01), Mirza et al.
patent: 5438668 (1995-08-01), Coon et al.
patent: 5442760 (1995-08-01), Rustad et al.
patent: 5459844 (1995-10-01), Eickemeyer et al.
patent: 5488710 (1996-01-01), Sato et al.
patent: 5499204 (1996-03-01), Barrera et al.
patent: 5513330 (1996-04-01), Stiles
patent: 5530825 (1996-06-01), Black et al.
patent: 5535347 (1996-07-01), Grochowski
patent: 5537629 (1996-07-01), Brown et al.
patent: 5544342 (1996-08-01), Dean
patent: 5551010 (1996-08-01), Iino et al.
patent: 5559975 (1996-09-01), Christie et al.
patent: 5560028 (1996-09-01), Sachs et al.
patent: 5566298 (1996-10-01), Boggs et al.
patent: 5586276 (1996-12-01), Grochowski et al.
patent: 5598544 (1997-01-01), Ohshima
patent: 5600806 (1997-02-01), Brown et al.
patent: 5625787 (1997-04-01), Mahin et al.
patent: 5644744 (1997-07-01), Mahin et al.
patent: 5644748 (1997-07-01), Utsunomiya et al.
patent: 5651125 (1997-07-01), Witt et al.
patent: 5689672 (1997-11-01), Witt et al.
patent: 5729707 (1998-03-01), Maki
patent: 5742791 (1998-04-01), Mahalingaiah et al.
patent: 5751981 (1998-05-01), Witt et al.
patent: 5758114 (1998-05-01), Johnson et al.
patent: 5758116 (1998-05-01), Lee et al.
patent: 5826053 (1998-10-01), Witt
patent: 5872943 (1999-02-01), Pickett et al.
patent: 5935238 (1999-08-01), Talcott et al.
patent: 5968163 (1999-10-01), Narayan et al.
patent: 5970235 (1999-10-01), Witt et al.
patent: 5987235 (1999-11-01), Tran
Intel, "Chapter 2: Microprocessor Architecture Overview," 1994, pp. 2-1 through 2-4.
Michael Slater, "AMD's K5 Designed to Outrun Pentium," Microprocessor Report, vol. 8, No. 14, Oct. 24, 1994, 7 pages.
Sebastian Rupley and John Clyman, "P6: The Next Step?," PC Magazine, Sep. 12, 1995, 16 pages.
Tom R. Halfhill, "AMD K6 Takes On Intel P6," BYTE, Jan. 1996, 4 pages.
"Intel Architecture Software Developer's Manual, vol. 1: Basic Architecture", Intel Corporation, Prospect IL, 1996, 1997, Chapter 8: Programming With The Intel MMX.TM. Technology, pp. 8-1 through 8-15.
Holstad, S., "Tutorial Tuesday: Decoding MMX" Jan. 14, 1997, Earthlink Network, Inc. copyright 1997, 5 pages (see http://www.earthlink.net/daily/Tuesday/MMX).
"Intel MMX.TM. Technology--Frequently Asked Questions" 6 pages (see http://www.intel.com/drg/mmx/support/faq/htm).
XP 000212140 Pleszkun, et al, "Structure Memory Access Architecture," Department of Computer Science, University of Wisconsin, IEEE 1983, pp. 461-471.
XP 000411690 Hua, et al, "Designing High-Performance Processors Using Real Address Prediction," IEEE Transactions on Computers 42 (1993) Sep., No. 9, New York, U.S., pp. 1146-1151.
XP 000337480 Baer, "An Effective On-Chip Preloading Scheme To Reduce Data Access Penalty," Department of Computer Science and Engineering, University of Washington, Seattle, WA, ACM, 1991, pp. 176-186.
Minagawa, et al, "Pre-Decoding Mechanism For Superscalar Architecture," IEEE Pacific Rim Conference on Communication, Computers and Signal Processing, May 9-10, 1991, pp. 21-24.
Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM Journal 1967, pp. 25-33.
Advanced Micro Devices , Inc.
An Meng-Ai T.
Kivlin B. Noel
Merkel Lawrence J.
Patel Gautam R.
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