Electrical computers and digital processing systems: processing – Processing control
Reexamination Certificate
2011-03-15
2011-03-15
Pan, Daniel (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
C712S225000
Reexamination Certificate
active
07908464
ABSTRACT:
A functional-level instruction-set computing (FLIC) architecture executes higher-level functional instructions such as lookups and bit-compares of variable-length operands. Each FLIC processing-engine slice has specialized processing units including a lookup unit that searches for a matching entry in a lookup cache. Variable-length operands are stored in execution buffers. The operand length and location in the execution buffer are stored in fixed-length general-purpose registers (GPRs) that also store fixed-length operands. A copy/move unit moves data between input and output buffers and one or more FLIC processing-engine slices. Multiple contexts can each have a set of GPRs and execution buffers. An expansion buffer in a FLIC slice can be allocated to a context to expand that context's execution buffer for storing longer operands. The FLIC engine is optimized to parse, lookup, and process long strings common in content-service requests and can offload file-server requests by looking up meta-data and pointers.
REFERENCES:
patent: 4229801 (1980-10-01), Whipple
patent: 4724517 (1988-02-01), May
patent: 4985848 (1991-01-01), Pfeiffer et al.
patent: 5127098 (1992-06-01), Rosenthal et al.
patent: 5148528 (1992-09-01), Fite et al.
patent: 5428779 (1995-06-01), Allegrucci et al.
patent: 5765216 (1998-06-01), Weng et al.
patent: 5768575 (1998-06-01), McFarland et al.
patent: 5793371 (1998-08-01), Deering
patent: 5802366 (1998-09-01), Row et al.
patent: 5835973 (1998-11-01), Kyuma et al.
patent: 5842004 (1998-11-01), Deering et al.
patent: 5854913 (1998-12-01), Goetz et al.
patent: 5870094 (1999-02-01), Deering
patent: 5909565 (1999-06-01), Morikawa et al.
patent: 5974547 (1999-10-01), Klimenko
patent: 6028610 (2000-02-01), Deering
patent: 6041407 (2000-03-01), Claar et al.
patent: 6128641 (2000-10-01), Fleck et al.
patent: 6182202 (2001-01-01), Muthukkaruppan
patent: 6304954 (2001-10-01), Munson
patent: 6349379 (2002-02-01), Gibson et al.
patent: 6490630 (2002-12-01), Poon et al.
patent: 6498571 (2002-12-01), Molloy
patent: 6532012 (2003-03-01), Deering
patent: 6545686 (2003-04-01), Fadden
patent: 6883068 (2005-04-01), Tsirigotis et al.
patent: 7254696 (2007-08-01), Mittal et al.
patent: 2001/0054140 (2001-12-01), Oberman et al.
patent: 2002/0038416 (2002-03-01), Fotland et al.
patent: 2003/0005268 (2003-01-01), Catherwood
patent: 2004/0193835 (2004-09-01), Devaney et al.
File, Definition, URL:http://searchexchange.techtarget.com/sdefintion/0,290660,sid43—gci212118,00.html Retrieved online Feb. 16, 2006.
Kharidia Mehul
Mertoguno J. Sukarno
Mittal Millind
Tripathy Tarun Kumar
Alacritech, Inc.
Lauer Mark A.
Pan Daniel
Silicon Edge Law Group LLP
LandOfFree
Functional-level instruction-set computer architecture for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Functional-level instruction-set computer architecture for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Functional-level instruction-set computer architecture for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2700338