Circuit for loading a memory rules for a fuzzy logic microproces

Circuit for time-sharing of configurable I/O pins

Circuit that implements semaphores in a multiprocessor...

Circuit to extract nonadjacent bits from data packets

Circuit to extract nonadjacent bits from data packets

Circuitry and method for performing branching without pipeline d

Circuits and methods for recovering link stack data upon...

Circuits, system, and methods for processing multiple data strea

Circuits, systems and methods for performing branch...

Circuits, systems, and methods for uniquely identifying a microp

Circular register arrays of a computer

Clear processing of a translation lookaside buffer with less wai

Clock architecture for multi-processor systems

Clustered architecture in a VLIW processor

Clustered superscalar processor with communication control...

Clustered superscalar processor with communication control...

Clustering stream and/or instruction queues for...

Coarse-grained look-up table architecture

Code interpretation using stack state information

Code segment default operation determination