Electrical computers and digital processing systems: processing – Architecture based instruction processing – Stack based computer
Reexamination Certificate
2006-08-11
2009-11-10
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Architecture based instruction processing
Stack based computer
Reexamination Certificate
active
07617383
ABSTRACT:
A stack processor comprises a data stack with a T register, an S register, and eight hardwired bottom registers which function in a circular repeating pattern. The stack processor also comprises a return stack containing an R register, and eight hardwired bottom registers which function in a circular repeating pattern. The circular register arrays described herein eliminate overflow and underflow stack conditions.
REFERENCES:
patent: 3757306 (1973-09-01), Boone
patent: 4107773 (1978-08-01), Gilbreath et al.
patent: 4215422 (1980-07-01), McCray et al.
patent: 4298932 (1981-11-01), Sams
patent: 4462074 (1984-07-01), Linde
patent: 4589067 (1986-05-01), Porter et al.
patent: 4593351 (1986-06-01), Hong et al.
patent: 4821231 (1989-04-01), Cruess et al.
patent: 4984151 (1991-01-01), Dujari
patent: 5029124 (1991-07-01), Leahy et al.
patent: 5053952 (1991-10-01), Koopman et al.
patent: 5218682 (1993-06-01), Frantz
patent: 5317735 (1994-05-01), Schomberg
patent: 5319757 (1994-06-01), Moore et al.
patent: 5359568 (1994-10-01), Livay et al.
patent: 5375238 (1994-12-01), Ooi
patent: 5377333 (1994-12-01), Nakagoshi et al.
patent: 5390304 (1995-02-01), Leach et al.
patent: 5396609 (1995-03-01), Schmidt et al.
patent: 5410723 (1995-04-01), Schmidt et al.
patent: 5440749 (1995-08-01), Moore et al.
patent: 5485624 (1996-01-01), Steinmetz et al.
patent: 5535393 (1996-07-01), Reeve et al.
patent: 5535417 (1996-07-01), Baji et al.
patent: 5551045 (1996-08-01), Kawamoto et al.
patent: 5572698 (1996-11-01), Yen et al.
patent: 5657485 (1997-08-01), Streitenberger et al.
patent: 5692197 (1997-11-01), Narad et al.
patent: 5706491 (1998-01-01), McMahan
patent: 5717943 (1998-02-01), Barker et al.
patent: 5727194 (1998-03-01), Shridhar et al.
patent: 5740463 (1998-04-01), Oshima et al.
patent: 5752259 (1998-05-01), Tran
patent: 5784602 (1998-07-01), Glass et al.
patent: 5826101 (1998-10-01), Beck et al.
patent: 5893148 (1999-04-01), Genduso et al.
patent: 5911082 (1999-06-01), Monroe et al.
patent: 6003128 (1999-12-01), Tran
patent: 6023753 (2000-02-01), Pechanek et al.
patent: 6038655 (2000-03-01), Little et al.
patent: 6085304 (2000-07-01), Morris et al.
patent: 6101598 (2000-08-01), Dokic et al.
patent: 6112296 (2000-08-01), Witt et al.
patent: 6145061 (2000-11-01), Garcia et al.
patent: 6145072 (2000-11-01), Shams et al.
patent: 6148392 (2000-11-01), Liu
patent: 6154809 (2000-11-01), Ikenaga et al.
patent: 6173389 (2001-01-01), Pechanek et al.
patent: 6178525 (2001-01-01), Warren
patent: 6219685 (2001-04-01), Story
patent: 6223282 (2001-04-01), Kang
patent: 6279101 (2001-08-01), Witt et al.
patent: 6353880 (2002-03-01), Cheng
patent: 6367005 (2002-04-01), Zahir et al.
patent: 6381705 (2002-04-01), Roche
patent: 6427204 (2002-07-01), Arimilli et al.
patent: 6449709 (2002-09-01), Gates
patent: 6460128 (2002-10-01), Baxter et al.
patent: 6507649 (2003-01-01), Tovander
patent: 6598148 (2003-07-01), Moore et al.
patent: 6665793 (2003-12-01), Zahir et al.
patent: 6725361 (2004-04-01), Rozas et al.
patent: 6825843 (2004-11-01), Allen et al.
patent: 6826674 (2004-11-01), Sato
patent: 6845412 (2005-01-01), Boike et al.
patent: 6959372 (2005-10-01), Hobson et al.
patent: 7028163 (2006-04-01), Kim et al.
patent: 7079046 (2006-07-01), Tanaka
patent: 7089438 (2006-08-01), Raad
patent: 7136989 (2006-11-01), Ishii
patent: 7155602 (2006-12-01), Poznanovic
patent: 7162573 (2007-01-01), Mehta
patent: 7197624 (2007-03-01), Pechanek et al.
patent: 7263624 (2007-08-01), Marchand et al.
patent: 7269805 (2007-09-01), Ansari et al.
patent: 2002/0010844 (2002-01-01), Noel et al.
patent: 2003/0028750 (2003-02-01), Hogenauer
patent: 2003/0065905 (2003-04-01), Ishii
patent: 2003/0217242 (2003-11-01), Wybenga et al.
patent: 2004/0003219 (2004-01-01), Uehara
patent: 2004/0059895 (2004-03-01), May et al.
patent: 2004/0107332 (2004-06-01), Fujii et al.
patent: 2004/0143638 (2004-07-01), Beckmann et al.
patent: 2004/0250046 (2004-12-01), Gonzalez et al.
patent: 2005/0027548 (2005-02-01), Jacobs et al.
patent: 2005/0114565 (2005-05-01), Gonzalez et al.
patent: 2005/0149693 (2005-07-01), Barry
patent: 2005/0206648 (2005-09-01), Perry et al.
patent: 2005/0223204 (2005-10-01), Kato
patent: 2006/0101238 (2006-05-01), Bose et al.
patent: 2006/0149925 (2006-07-01), Nguyen et al.
patent: 2006/0248317 (2006-11-01), Vorbach et al.
patent: 2006/0259743 (2006-11-01), Suzuoki
patent: 2007/0113058 (2007-05-01), Tran et al.
patent: 2007/0192504 (2007-08-01), Moore
patent: 0156654 (1985-10-01), None
patent: 0227319 (1987-07-01), None
patent: 0992896 (2000-04-01), None
patent: 1182544 (2002-02-01), None
patent: 1821211 (2007-08-01), None
patent: WO97/15001 (1997-04-01), None
patent: WO00/42506 (2000-07-01), None
patent: WO 02/50700 (2002-06-01), None
patent: WO02/088936 (2002-11-01), None
patent: WO03/019356 (2003-03-01), None
patent: WO2005/091847 (2005-10-01), None
Koopman Jr.,Phillp. , Stack Computers the new wave published by Ellis Horwood, 1989.,pp. 1-232.
Sharangpani, H etal. , Itanium Processor Microarchitecture. IEEE, 2000.pp. 24-43.
Scholz.T etal. An Improved Dynamic Register Array Concept for High-Performance RISC Processors, IEEE 1995, pp. 181-190.
Ambric's New Parallel Processor; Globally Asynchronous Architecture Eases Parallel Programming; Tom R. Halfhill; Microprocessor Report, Scottsdale, Az; Oct. 10, 2006; pp. 1-9.
An Asynchronous Array of Simple Processors for DSP Applications; Zhiyi et al., Yu; IEEE International Conference Digest of Technical Papers, Feb. 6-9, 2006; pp. 1696-1705.
An Instruction Buffer for Low-Power DSP; Brackenbury, M. L. L.; Advanced Research In Asynchronous Circuits And Systems, 2000 (ASYNC 2000) Proceedings, Sixth international Symposium On Eilat, Israel, Apr. 2-6, 2000; Los Alamitos, CA, USA; IEEE Comput. Soc., US; Apr. 2, 2000. pp. 176-186.
An Ultra Low-Power Processor for Sensor Networks; Ekanayake et al., V.; Sigplan Notices ACM, vol. 39, No. 11, Nov. 2004; pp. 27-36.
ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor; Renaudin et al.; Proceedings. International Symposium On Advanced Research In Asychronous Circuits And Systems; Jan. 1, 1989, p. 2231.
BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous Processor; Ekanayake et al., V.N.; Asynchronous Circuits & Systems, Mar. 14-16, 2005; pp. 144-154.
B16—Ein Forth Prozessor im FPGA; Bernd Paysan; INET (Online); Feb. 2, 2003, XP002490986; Retreived from the Internet: url:http://www.jwdt.com/{paysan/b16.pdf> p. 1.
C18 Colorforth Compiler; Chuck Moore; Euroforth 2001 (Online); Nov. 26, 2001, XP002490985, Schloss Dagstuhl, Saarland, Germany; Retreived from the Internet: url:http://www.complang.tuwien.ac.at/anton/euroforth/ef01/moore01a.pdf> p. 1.
Computer Archtecture: a Quantitative Approach; Hennessy et al., John L.; Morgan Kaufmann Publishers, 3rdEdition, 2003; p. 98.
Connection Machine Model CM-5 System Overview; Palmer et al., Thinking Machine Corp., Cambridge, Mass., IEEE Jul. 1992, pp. 474-483.
Datawave: A Single-Chip Multiprocessor for Video Applications; Schmidt et al., U.; IEEE Micro, IEEE Service Center, vol. 11, No. 3, Jun. 1, 1991; pp. 22-25, 88.
Energy Characterization of a Tiled Architecture Processor with On-Chip Networks; Kim, J.S.; Proceedings of the 2003 International Symposium on Low Power Electronics & Design, Aug. 25-27 2003; pp. 424-427.
Enhanced Serial Port on the 83C51FA, Intel, Nov. 1987.
Flits: Pervasive Computing for Processor and Memory Constrained Systems, Majurski et al., NIST, pp. 31-38; not dated.
Forth Session—The Evolution of Forth, Rather et al., Sigplan Notices USA, vol. 28, No. 3, Mar. 1993, pp. 177-199.
Functionally Asynchronous Array Processor for Morphological Filtering of Greyscale Images; Robin et al., F.; IEEE Proceedings: Computers and Digital Techniques, vol. 143, No. 5, Sep. 24, 1996; pp. 273-281.
IEEE Standard for Boot(Initialization Configuration)Firmware: Core Requirements and Practices, IEEE Std 1275; 1994.
Introduction to Java's Architecture, Bill Venners, Artima.com; Jan. 8, 1999, pp. 1-10.
iWarp: A 100-MPOS, LIW Micr
Fox Jeffrey Arthur
Moore Charles H.
Rible John W.
Coleman Eric
Henneman & Associates PLC
Henneman, Jr. Larry E.
VNS Portfolio LLC
LandOfFree
Circular register arrays of a computer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circular register arrays of a computer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circular register arrays of a computer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4140853