Selecting next instruction line buffer stage based on...
Selecting register or previous instruction result bypass as sour
Selecting subroutine return mechanisms
Selecting subroutine return mechanisms
Selection from multiple fetch addresses generated concurrently i
Selection of decoder output from two different length...
Selection of link and fall-through address using a bit in a...
Selective bypassing of a multi-port register file
Selective canonizing on mode transitions
Selective execution of deferred instructions in a processor...
Selective flush of shared and other pipeline stages in a...
Selective hardware lock disabling
Selective hardware lock disabling
Selective instruction breakpoint generation based on a count...
Selective interrupt suppression
Selective MISR data accumulation during exception processing
Selective postponement of branch target buffer (BTB) allocation
Selective signalling of later reserve location memory fault...
Selective suppression of register renaming
Selective vertical and horizontal dependency resolution via...