Selection of decoder output from two different length...

Details Selection of decoder output from two different length... Selection of decoder output from two different length...

2005-05-03

2005-05-03

Kim, Kenneth S. (Department: 2181)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding by plural parallel decoders

C712S043000, C712S210000

Reexamination Certificate

active

06889313

ABSTRACT:
A decode unit comprises first and second decoders respectively connected to receive bit sequences of first and second predetermined lengths. The first and second decoders operate in parallel to generate respective outputs. A switch selects one of the outputs in dependence on an instruction mode of the processor which governs the length of the bit sequence which is actually required to be decoded.

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patent: 1 442 459 (1976-07-01), None
patent: 2 289 353 (1995-11-01), None
patent: WO 9914669 (1999-03-01), None
“What's the Difference Between RISC and CISC?”.

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