Selection from multiple fetch addresses generated concurrently i

Details Selection from multiple fetch addresses generated concurrently i Selection from multiple fetch addresses generated concurrently i

1997-06-19

1999-08-10

Kim, Kenneth S.

Electrical computers and digital processing systems: processing

Instruction fetching

Of multiple instructions simultaneously

712237, 712239, G06F 932

Patent

active

059352388

ABSTRACT:
A microprocessor is provided with an instruction fetch mechanism that simultaneously predicts multiple control-flow instructions. The instruction fetch unit farther is capable of handling multiple types of control-flow instructions. The instruction fetch unit uses predecode data and branch prediction data to select the next instruction fetch bundle address. If a branch misprediction is detected, a corrected branch target address is selected as the next fetch bundle address. If no branch misprediction occurs and the current fetch bundle includes a taken control-flow instruction, then the next fetch bundle address is selected based on the type of control-flow instruction detected. If the first taken control-flow instruction is a return instruction, a return address from the return address stack is selected as the next fetch bundle address. If the first taken control-flow instruction is an unconditional branch or predicted taken conditional branch, a predicted branch target address is selected as the next fetch bundle address. If no branch misprediction is detected and the current fetch bundle does not include a taking control-flow instruction, then a sequential address is selected as the next fetch bundle address.

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Yeh, et al, "A Comprehensive Instruction Fetch Mechanism for a Processor Supporting Speculative Execution," Department of Electrical Engineering and Computer Science, University of Michigan IEEE Publication 1992, pp. 129-139.

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